H10D 84/854
Comprising arrangements for preventing bipolar actions between the different igfet regions
Official title: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
H10D84/854 (Comprising arrangements for preventing bipolar actions between the different igfet regions) appears on 641 US grants and 507 published applications in this corpus.
Search patents in H10D- Granted patents
- 641
- Published applications
- 507
- Assignees
- 208
- Inventors
- 994
- Latest grant
- 11 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 7 | 0 |
| 1980 | 2 | 0 |
| 1981 | 3 | 0 |
| 1982 | 3 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 9 | 0 |
| 1987 | 15 | 0 |
| 1988 | 8 | 0 |
| 1989 | 7 | 0 |
| 1990 | 12 | 0 |
| 1991 | 9 | 0 |
| 1992 | 7 | 0 |
| 1993 | 7 | 0 |
| 1994 | 8 | 0 |
| 1995 | 13 | 0 |
| 1996 | 6 | 0 |
| 1997 | 14 | 0 |
| 1998 | 15 | 0 |
| 1999 | 20 | 0 |
| 2000 | 16 | 0 |
| 2001 | 20 | 2 |
| 2002 | 19 | 20 |
| 2003 | 10 | 17 |
| 2004 | 15 | 18 |
| 2005 | 17 | 12 |
| 2006 | 6 | 20 |
| 2007 | 22 | 32 |
| 2008 | 9 | 31 |
| 2009 | 13 | 18 |
| 2010 | 28 | 20 |
| 2011 | 21 | 18 |
| 2012 | 20 | 17 |
| 2013 | 22 | 26 |
| 2014 | 21 | 23 |
| 2015 | 22 | 21 |
| 2016 | 26 | 21 |
| 2017 | 25 | 15 |
| 2018 | 18 | 15 |
| 2019 | 15 | 18 |
| 2020 | 22 | 22 |
| 2021 | 15 | 20 |
| 2022 | 16 | 25 |
| 2023 | 12 | 23 |
| 2024 | 17 | 20 |
| 2025 | 16 | 18 |
| 2026 | 7 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Planar MOSFET with light, regular and heavily doped regions11 Aug 2026US 12,707,668 B2Invention And Collaboration Laboratory Pte. Ltd.
- Semiconductor device11 Aug 2026US 12,707,710 B2Fuji Electric Co., Ltd.
- Amorphized subfins using backside implantation11 Aug 2026US 12,707,712 B2Intel Corporation
- Embedded semiconductor region for a latch-up susceptibility improvement21 Jul 2026US 12,690,266 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Methods of improving PMOS transistor performance23 Jun 2026US 12,666,695 B2APPLIED Materials.Inc.
- Embedded semiconductor region for latch-up susceptibility improvement8 Oct 2026US 2026/0314060 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Gate isolation feature in cfet devices20 Aug 2026US 2026/0247689 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Latch-up circuit capable of suppressing trigger, and structure of semiconductor substrate comprising latch-up circuit capable of suppressing trigger16 Jul 2026US 2026/0206327 A1Lx Semicon Co., Ltd.
- Integrated circuit device4 Jun 2026US 2026/0156935 A1Samsung Electronics Co., Ltd.
- Semiconductor device with backside isolation ring for latch-up immunity7 May 2026US 2026/0129964 A1International Business Machines Corporation
Most cited
By later US patents
- Circuit and method for PMOS device N-well bias control175US 6,377,112 B1Semiconductor Components Industries, LLC · 2002
- Manufacturing method for semiconductor devices with source/drain formed in substrate projection.118US 5,391,506 AKawasaki Steel Corporation · 1995
- Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates115US 7,818,702 B2International Business Machines Corporation · 2010
- Latchup-free fully-protected CMOS on-chip ESD protection circuit99US 5,637,900 AIndustrial Technology Research Institute · 1997
- Submicron lightly doped field effect transistors95US 4,949,136 AUniversity of Connecticut · 1990