Embedded semiconductor region for a latch-up susceptibility improvement
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien Yao Huang, Yu-Ti Su
Life of this patent
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Abstract
The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.
Claims20
A structure, comprising:
- a p-type region on a substrate and doped with a first doping concentration;
- an n-type well on and horizontally surrounded completely by the p-type region, wherein the n-type well is doped with a second doping concentration;
- a metal oxide semiconductor (MOS) device comprising first and second source/drain regions in the n-type well;
- an embedded semiconductor region (ESR) on the p-type region and surrounding the n-type well, wherein a third doping concentration of the ESR is less than the first doping concentration of a portion of the p-type region in direct contact with the ESR, wherein a horizontal interface between the ESR and the p-type region is in contact with a vertical interface between the ESR and the p-type region, and wherein the horizontal interface extends under the n-type well;
- and
- a p-type contact region on the p-type region and having a fourth doping concentration greater than the first doping concentration.
A structure, comprising:
- a first p-type region on a substrate;
- a first n-type region on the first p-type region;
- a metal oxide semiconductor (MOS) device on the first n-type region, wherein the MOS device comprises first and second source/drain regions in the first n-type region;
- a second n-type region in the first n-type region, wherein doping concentrations of the first n-type region and the second n-type region are different;
- a second p-type region on the first p-type region, wherein doping concentrations of the first p-type region and the second p-type region are different;
- an embedded semiconductor region (ESR) surrounding the first n-type region, wherein a doping concentration of the ESR is lower than the doping concentrations of the first p-type region and the first n-type region, wherein a portion of the first p-type region is under the ESR, and wherein another portion of the first p-type region is between the ESR and the second p-type region;
- and
- an intrinsic ESR surrounding the ESR and isolated from the ESR, wherein a horizontal interface between the intrinsic ESR and the first p-type region is coplanar with a horizontal interface between the ESR and the first p-type region.
A method, comprising:
- forming an n-type well on a p-type region of a substrate;
- doping a portion of the n-type well to form an n-type region in the n-type well;
- forming a metal oxide semiconductor (MOS) device on the n-type well and isolated from the p-type region;
- forming a p-type contact region in the p-type region;
- forming an embedded semiconductor region (ESR) in direct contact with and surrounded by the p-type region, completely surrounding the n-type well along horizontal directions, and having a doping concentration less than those of the n-type well or the p-type region;
- and
- forming another ESR surrounding and isolated from the ESR, wherein a first horizontal interface between the ESR and the p-type region is coplanar with a second horizontal interface between the other ESR and the p-type region.
Dependencies are inferred from the claim text.