Gate isolation feature in cfet devices

A method of forming a semiconductor device, comprising:

• forming a structure having a bottom region and a top region, the bottom region having a first plurality of channels for forming a first type transistor, the top region having a second plurality of channels for forming a second type transistor, wherein the top and the bottom regions are separated by a channel isolation layer;
• depositing a first gate metal over the structure and wrapping around each channel of the first and the second plurality of channels;
• etching back the first gate metal to expose each channel of the second plurality of channels;
• depositing a gate isolation layer on the etched-back first gate metal, wherein the gate isolation layer includes amorphous boron nitride (BN), hexagonal BN, SiBN, BCN, SiBCN, or combinations thereof;
• and
• depositing a second gate metal on the gate isolation layer and wrapping around each channel of the second plurality of channels.

A semiconductor device, comprising:

• a first stack of semiconductor channels over a substrate;
• a first gate metal over the substrate and wrapping around the first stack of semiconductor channels;
• a channel isolation layer over a topmost semiconductor channel of the first stack of semiconductor channels;
• a gate isolation layer adjacent the channel isolation layer and over the first gate metal;
• a second stack of semiconductor channels over the channel isolation layer;
• and
• a second gate metal over the gate isolation layer and wrapping around the second stack of semiconductor channels,
• wherein the gate isolation layer has a dielectric constant lower than 7 and is disposed vertically between the first gate metal and the second gate metal.