Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates

A design structure embodied in a non-transient machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:

• a semiconductor-on-insulator substrate including a semiconductor layer with a top surface, a bulk semiconductor region of a first conductivity type underlying the semiconductor layer, and an insulating layer between the semiconductor layer and the bulk semiconductor region;
• an opening having a base intersecting the bulk semiconductor region and a plurality of sidewalls extending from the top surface of the semiconductor layer through the semiconductor layer and the insulating layer to the base;
• a conductive region in the bulk semiconductor region at a location proximate to the base of the opening, said conductive region having a second conductivity type opposite to said first conductivity type;
• a first epitaxial layer composed of a semiconductor material and disposed in the opening, the conductive semiconductor material of the first epitaxial layer doped with the first conductivity type at a first doping concentration;
• and
• a second epitaxial layer composed of the semiconductor material and disposed in the opening and separated from the first conductive region by the first epitaxial layer, the semiconductor material of the second epitaxial layer doped with the first conductivity type at a second doping concentration lower than the first doping concentration or doped with the second conductivity type.