Planar MOSFET with light, regular and heavily doped regions
AssigneeInvention And Collaboration Laboratory Pte. Ltd.
InventorsChao-Chun Lu, Li-Ping Huang
Life of this patent
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Abstract
A transistor structure includes a semiconductor substrate, a gate region, a first trench, a first isolation region and a first conductive region. The semiconductor substrate is with an original semiconductor surface. The gate region is over the semiconductor surface. The first trench is formed below the original semiconductor surface. The first isolation region is in the first trench. The first conductive region is formed with a first doping region and a second doping region; wherein the first doping region is within the semiconductor substrate and the second doping region is formed outside from the semiconductor substrate.
Claims13
A transistor structure comprising:
- a semiconductor substrate with an original semiconductor surface;
- a gate region over the original semiconductor surface a first trench formed below the original semiconductor surface;
- a first isolation region in the first trench;
- and
- a first conductive region with a first doping region and a second doping region;
- wherein the first doping region is formed by thermally annealing a deposited in-situ doped semiconductor layer, and the second doping region is formed by selective growth based on the first doping region.
A transistor structure comprising:
- a semiconductor substrate with an original semiconductor surface;
- a first transistor comprising:
- a first gate region over the original semiconductor surface;
- a first trench formed below the original semiconductor surface;
- a first isolation region in the first trench;
- and
- a first conductive region with a first doping region and a second doping region;
- wherein the first doping region is within the semiconductor substrate and the second doping region is outside the semiconductor substrate;
- and
- a second transistor comprising:
- a second gate region over the original semiconductor surface;
- a second trench formed below the original semiconductor surface;
- a second isolation region in the second trench;
- and
- a second conductive region with a third doping region and a fourth doping region;
- wherein the third doping region is within the semiconductor substrate and the fourth doping region is outside the semiconductor substrate;
- wherein a doping concentration of the first doping region is different from that of third doping region;
- the first doping region is formed by thermally annealing a first deposited in-situ doped semiconductor layer;
- the third doping region is formed by thermally annealing a second deposited in-situ doped semiconductor layer;
- and a doping concentration of the first deposited in-situ doped semiconductor layer is different from a doping concentration of the second deposited in-situ doped semiconductor layer.
A transistor structure comprising:
- a semiconductor substrate with an original semiconductor surface;
- a first transistor comprising:
- a first gate region over the original semiconductor surface;
- a first trench formed below the original semiconductor surface;
- a first isolation region in the first trench;
- and
- a first conductive region with a first doping region and a second doping region;
- and
- a second transistor comprising:
- a second gate region over the original semiconductor surface;
- a second trench formed below the original semiconductor surface;
- a second isolation region in the second trench;
- and
- a second conductive region with a third doping region and a fourth doping region;
- wherein the first doping region and third doping region are formed simultaneously by a thermal annealing process;
- and the first doping region is formed by thermally annealing a first deposited in-situ doped semiconductor layer, and the third doping region is formed by thermally annealing a second deposited in-situ doped semiconductor layer.
Dependencies are inferred from the claim text.