Submicron lightly doped field effect transistors
AssigneeUniversity of Connecticut
InventorFaquir C. Jain
Life of this patent
Estimating the term…
Abstract
A lightly doped field effect transistor has a central gate portion and source and drain portions spaced to opposite sides thereof and each having a heavily doped contact section and a sidewall spacer portion between the gate portion and contact section. Each of the source and drain portions also has a lightly doped sheath with a first portion extending to a first depth about the sides of and below the contact section, and an extension of lesser depth extending under the spacer portion to the gate portion, thus providing a stepped configuration for the sheath in cross section. The sheaths have an impurity doping concentration which is 10.sup.2 -10.sup.4 lower than the impurity doping concentration in the contact sections.
Claims6
A silicon lightly doped field effect transistor having:
- (a) a central gate portion;
- (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section;
- and
- (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, said sheaths having an impurity doping concentration 10.sup.2 - 4 lower than the impurity doping concentration in the heavily doped contact sections.
A CMOS transistor pair structure comprising a spaced lightly doped field effect pair of transistors each having:
- (a) a central gate portion;
- (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section:
- and
- (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spaced portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, the lightly doped sheaths of one of said transistors being of n.sup.- conductivity type and 10.sup.2 -10.sup.4 lower in impurity doping concentration than the heavily doped n.sup.+ sections, the lightly doped sheaths of the other of said transistors being of p.sup.- conductivity type and 10.sup.2 -10.sup.4 lower in impurity doping concentration than the heavily doped p.sup.+ sections.
Dependencies are inferred from the claim text.