G11C 16/3427
Circuits or methods to prevent or reduce disturbance of the state of
Official title: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
G11C16/3427 (Circuits or methods to prevent or reduce disturbance of the state of) appears on 2,202 US grants and 2,294 published applications in this corpus.
Search patents in G11C- Granted patents
- 2,202
- Published applications
- 2,294
- Assignees
- 234
- Inventors
- 2,221
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 1 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 6 | 0 |
| 1997 | 8 | 0 |
| 1998 | 14 | 0 |
| 1999 | 19 | 0 |
| 2000 | 17 | 0 |
| 2001 | 21 | 5 |
| 2002 | 15 | 18 |
| 2003 | 10 | 25 |
| 2004 | 24 | 28 |
| 2005 | 24 | 36 |
| 2006 | 32 | 40 |
| 2007 | 46 | 73 |
| 2008 | 68 | 108 |
| 2009 | 64 | 84 |
| 2010 | 65 | 74 |
| 2011 | 79 | 62 |
| 2012 | 69 | 60 |
| 2013 | 50 | 74 |
| 2014 | 87 | 128 |
| 2015 | 133 | 116 |
| 2016 | 146 | 125 |
| 2017 | 134 | 99 |
| 2018 | 122 | 102 |
| 2019 | 132 | 131 |
| 2020 | 149 | 130 |
| 2021 | 123 | 117 |
| 2022 | 112 | 129 |
| 2023 | 104 | 152 |
| 2024 | 141 | 143 |
| 2025 | 112 | 110 |
| 2026 | 64 | 125 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Apparatus containing memory array structures having multiple sub-blocks, and operation of such apparatus25 Aug 2026US 12,718,883 B2Micron Technology, Inc.
- Read disturb management25 Aug 2026US 12,718,895 B2Micron Technology, Inc.
- Bias voltage control for sub-block groups in a memory device8 Oct 2026US 2026/0311766 A1Micron Technology, Inc.
- Read method of memory device and memory device therefore1 Oct 2026US 2026/0301845 A1Macronix International Co., Ltd.
- Modulation of source voltage in nand-flash array read24 Sep 2026US 2026/0290469 A1Intel NDTM US LLC
- Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory17 Sep 2026US 2026/0279460 A1Silicon Motion, Inc.
- Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory17 Sep 2026US 2026/0279461 A1Silicon Motion, Inc.
Most cited
By later US patents
- Multi-state memory1,008US 6,222,762 B1SanDisk Corporation · 2001
- Variable programming of non-volatile memory725US 7,020,017 B2SanDisk Corporation · 2006
- Programming method to reduce gate coupling interference for non-volatile memory460US 7,400,532 B2Micron Technology, Inc. · 2008
- Architecture and method for NAND flash memory438US 7,372,715 B2Micron Technology, Inc. · 2008
- System that compensates for coupling based on sensing a neighbor using coupling423US 7,602,647 B2SanDisk Corporation · 2009