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US 7,372,715 B2Granted
Architecture and method for NAND flash memory
AssigneeMicron Technology, Inc.
InventorJin-Man Han
Life of this patent
Estimating the term…
Abstract
A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.
Claims14
A memory array, comprising:
- an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines;
- and
- a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.
A memory device, comprising:
- an array of non-volatile memory cells accessed by bitlines and word lines;
- circuitry for control and/or access of the array of non-volatile memory cells;
- and
- a plurality of sense amplifiers, each sense amplifier connected to two bitlines, an even and an odd bitline, each even bitline positioned in a first portion of the array and each odd bitline positioned in a second portion of the array separate from the first portion of the array.
1 more element
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines;
- and
- a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.
4 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines;
- and
- a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.
4 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:
- an array of non-volatile memory cells arranged in rows and columns and accessed by bitlines and word lines;
- and
- a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.
3 more elements
A processing system, comprising:
- a processor;
- and
- a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells arranged in rows and columns and accessed by bitlines and word lines;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections;
- and
- a plurality of sense amplifiers, each sense amplifier connected to an even bitline and an odd bitline, wherein each even bitline is positioned in a first portion of the array and each odd bitline is positioned in a second portion of the array separate from the first portion of the array.
5 more elements
Dependencies are inferred from the claim text.