Apparatus containing memory array structures having multiple sub-blocks, and operation of such apparatus

An apparatus, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a data line;
• and
• a controller configured to cause the apparatus to:
• program a first set of field-effect transistors between a first string of series-connected memory cells and a data line to have a complementary binary permutation of two threshold voltages to a binary permutation of two threshold voltages of a second set of field-effect transistors between the first set of field-effect transistors and the data line;
• program a third set of field-effect transistors between a second string of series-connected memory cells and the data line to have a complementary binary permutation of two threshold voltages to a binary permutation of two threshold voltages of a fourth set of field-effect transistors between the third set of field-effect transistors and the data line;
• program a fifth set of field-effect transistors between the first string of series-connected memory cells and the first set of field-effect transistors to have a first threshold voltage and program a sixth set of field-effect transistors between the first string of series-connected memory cells and the fifth set of field-effect transistors to have a second threshold voltage lower than the first threshold voltage;
• and
• program a seventh set of field-effect transistors between the second string of series-connected memory cells and the third set of field-effect transistors to have the second threshold voltage and program an eighth set of field-effect transistors between the second string of series-connected memory cells and the seventh set of field-effect transistors to have the first threshold voltage.