US 12,717,474 B2 · Memory device, a memory system and an operation method

Abstract

A memory device includes a memory array and a control logic coupled to the memory array. The memory array includes memory blocks. Each memory block includes memory cell strings, and each memory cell string includes a first memory cell, second memory cells, and a third memory cell. The second memory cells are between the first memory cell and the third memory cell. The first memory cell is coupled to a bit line, the third memory cell is coupled to a source line, the first memory cell is coupled with a first dummy word line, the second memory cells are respectively coupled with second word lines, and the third memory cell is coupled with a third word line. The control logic is configured to prior to programming the second memory cells of a memory block of the memory blocks, determine a first average value of threshold voltages of third memory cells in the memory block, determine a difference value between the first average value and a first reference value, and based on the difference value less than a second reference value, program third memory cells in the memory block, such that the difference is greater than or equal to the second reference.

Claims20

Dependent claims

A memory device, comprising:

a memory array, wherein the memory array comprises memory blocks, each memory block includes memory cell strings, and each memory cell string includes a first memory cell coupled with a first word line, second memory cells respectively coupled with second word lines, and a third memory cell coupled with a third word line, wherein the second memory cells are between the first memory cell and the third memory cell, the first memory cell is adjacent to a bit line, and the third memory cell is a memory cell closest to a source line and is a dummy cell configured to be selectively programmed based on threshold voltages of the third memory cells in a memory block of the memory blocks;
and
a control logic coupled to the memory array and configured to:
based on a comparison of a first average value of the threshold voltages of the third memory cells and a target value, selectively perform a first program operation on the third memory cells coupled with the third word line in the memory block of the memory blocks;
and
perform a second program operation on the second memory cells in the memory block, wherein when the first program operation is performed on the third memory cells, the first program operation is performed before the second program operation on the second memory cells.

3 more elements

An operation method of a memory device, wherein the memory device comprises a memory array, wherein the memory array comprises memory blocks, each memory block includes memory cell strings, and each memory cell string includes a first memory cell coupled with a first word line, second memory cells respectively coupled with second word lines, and a third memory cell coupled with a third word line, wherein the second memory cells are between the first memory cell and the third memory cell, the first memory cell is adjacent to a bit line, and the third memory cell is a memory cell closest to a source line and is a dummy cell configured to be selectively programmed based on threshold voltages of the third memory cells in a memory block of the memory blocks, the operation method comprises:

based on a comparison of a first average value of the threshold voltages of the third memory cells and a target value, selectively performing a first program operation on the third memory cells coupled with the third word line in the memory block of the memory blocks;
and
performing a second program operation on the second memory cells in the memory block, wherein when the first program operation is performed on the third memory cells, the first program operation is performed before the second program operation on the second memory cells.

Dependencies are inferred from the claim text.

Memory device, a memory system and an operation method

Life of this patent

Memory device, a memory system and an operation method

Life of this patent

Abstract

Claims20