Modulation of source voltage in nand-flash array read
AssigneeIntel NDTM US LLC
InventorNarayanan RAMANAN
Life of this patent
Estimating the term…
Abstract
Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source volage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
Claims20
A storage device, comprising:
- a storage array including one or more strings of memory cells coupled with a source line;
- and
- logic circuit coupled to the one or more strings of memory cells and configured to perform a read operation by at least:
- sequentially alternating between array idle operations and active sensing operations on the storage array;
- and
- alternately biasing the source line to a first source voltage during the array idle operations and to a second source voltage during the active sensing operations.
A solid state drive (SSD), comprising:
- input/output (I/O) interface circuitry to couple with a host, the I/O interface circuitry to receive a request for a read operation;
- and
- one or more dies including:
- a storage array including one or more strings of memory cells coupled with a source line;
- and
- logic circuit coupled to the one or more strings of memory cells and configured to perform a read operation by at least:
- sequentially alternating between array idle operations and active sensing operations on the storage array;
- and
- alternately biasing the source line to a first source voltage during the array idle operations and to a second source voltage during the active sensing operations.
A system, comprising:
- a processor;
- and
- a storage device further including a storage array and logic circuit, the storage array further including one or more strings of memory cells coupled with a source line, the logic circuit coupled to the one or more strings of memory cells and configured to perform a read operation by at least:
- sequentially alternating between array idle operations and active sensing operations on the storage array;
- and
- alternately biasing the source line to a first source voltage during the array idle operations and to a second source voltage during the active sensing operations.
Dependencies are inferred from the claim text.