H10W 72/255
Of outermost layers of multilayered bumps
Official title: {of outermost layers of multilayered bumps, e.g. material of a coating}
H10W72/255 (Of outermost layers of multilayered bumps) appears on 1,369 US grants and 1,575 published applications in this corpus.
Search patents in H10W- Granted patents
- 1,369
- Published applications
- 1,575
- Assignees
- 395
- Inventors
- 2,420
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 0 | 0 |
| 1995 | 4 | 0 |
| 1996 | 2 | 0 |
| 1997 | 4 | 0 |
| 1998 | 13 | 0 |
| 1999 | 25 | 0 |
| 2000 | 14 | 0 |
| 2001 | 20 | 18 |
| 2002 | 22 | 28 |
| 2003 | 14 | 22 |
| 2004 | 22 | 35 |
| 2005 | 19 | 39 |
| 2006 | 23 | 68 |
| 2007 | 31 | 51 |
| 2008 | 22 | 46 |
| 2009 | 31 | 47 |
| 2010 | 53 | 56 |
| 2011 | 62 | 87 |
| 2012 | 63 | 71 |
| 2013 | 77 | 86 |
| 2014 | 69 | 91 |
| 2015 | 74 | 106 |
| 2016 | 85 | 94 |
| 2017 | 108 | 104 |
| 2018 | 87 | 78 |
| 2019 | 87 | 87 |
| 2020 | 71 | 69 |
| 2021 | 61 | 76 |
| 2022 | 54 | 54 |
| 2023 | 54 | 43 |
| 2024 | 34 | 48 |
| 2025 | 34 | 38 |
| 2026 | 18 | 33 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Metal pillar for conductive connection6 Oct 2026US 12,757,750 B2Duksan Hi-Metal Co., Ltd.
- Semiconductor package and method of manufacturing the same6 Oct 2026US 12,757,796 B2Samsung Electronics Co., Ltd.
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Ball grid array assembly using a solder paste mix and method of using a solder paste dip11 Aug 2026US 12,707,987 B1Frontgrade Technologies Inc.
- Semiconductor package and manufacturing method therefor11 Aug 2026US 12,708,031 B2LG Innotek Co., Ltd.
- Microelectronics package with hybrid connection to a substrate to enable reuse8 Oct 2026US 2026/0314461 A1NXP B. V.
- Semiconductor packages with separately plated metal pillars1 Oct 2026US 2026/0305410 A1Texas Instruments Incorporated
- Semiconductor device assembly interconnection pillars and associated methods17 Sep 2026US 2026/0282991 A1Micron Technology, Inc.
- Connecting pillar17 Sep 2026US 2026/0282992 A1Duksan Hi-Metal Co., Ltd.
- Light emitting module and light system including the same10 Sep 2026US 2026/0271471 A1Seoul Viosys Co., Ltd.
Most cited
By later US patents
- Package of integrated circuits and vertical integration749US 6,322,903 B1Tru-Si Technologies, Inc. · 2001
- Sockets for electronic components and methods of connecting to electronic components453US 5,772,451 AForm Factor, Inc. · 1998
- Method of planarizing tips of probe elements of a probe card assembly397US 5,974,662 AFormFactor, Inc. · 1999
- Flexible contact structure with an electrically conductive shell340US 5,917,707 AFormFactor, Inc. · 1999
- Packaging of integrated circuits and vertical integration329US 6,693,361 B1Tru-Si Technologies, Inc. · 2004