Packaging of integrated circuits and vertical integration
AssigneeTru-Si Technologies, Inc.
InventorsOleg Siniaguine, Sergey Savastiouk
Life of this patent
Estimating the term…
Abstract
A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
Claims29
A structure comprising:
- a first semiconductor wafer having one or more first through holes going through the first semiconductor wafer at a boundary of at least one die which is part of the first semiconductor wafer and which comprises at least a portion of a semiconductor substrate, the one or more first through holes being located outside of the die;
- and
- a second semiconductor wafer bonded to the first semiconductor wafer.
A structure comprising:
- a first chip or wafer comprising a first substrate made of a semiconductor or insulating material, one or more through holes that go through the first substrate, a first contact at each said through hole, wherein the first chip or wafer comprises, in each said through hole, at least a part of at least one conductive layer having a portion protruding from the first chip or wafer through the through hole, wherein the first contact at the through hole comprises at least a part of the protruding portion, the conductive layer extending laterally outward from the protruding portion as the conductive layer moves into the through hole from the protruding portion;
- and
- a wiring substrate to which the first contacts are directly attached, wherein the wiring substrate does not include a semiconductor substrate, the wiring substrate having one or more conductive lines for providing electrical connection to the first chip or wafer.
A structure comprising:
- a first semiconductor wafer comprising a semiconductor die, the first semiconductor wafer having a via going through the first semiconductor wafer, the via laterally completely surrounding the die;
- and
- a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer being bonded to the die.
A structure comprising:
- a first wafer comprising a semiconductor substrate, the first wafer having a surface having one or more scribe lines thereon;
- at least one via going through the semiconductor substrate, the via being positioned on the one or more scribe lines;
- and
- a second wafer comprising a semiconductor substrate, the second wafer being bonded to the first wafer.
Dependencies are inferred from the claim text.