H10W 72/01359
By planarisation
Official title: {by planarisation, e.g. chemical-mechanical polishing [CMP]}
H10W72/01359 (By planarisation) appears on 35 US grants and 50 published applications in this corpus.
Search patents in H10W- Granted patents
- 35
- Published applications
- 50
- Assignees
- 22
- Inventors
- 103
- Latest grant
- 28 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2011 | 0 | 2 |
| 2012 | 1 | 2 |
| 2013 | 2 | 1 |
| 2014 | 0 | 0 |
| 2015 | 2 | 2 |
| 2016 | 1 | 2 |
| 2017 | 1 | 4 |
| 2018 | 2 | 2 |
| 2019 | 3 | 1 |
| 2020 | 2 | 5 |
| 2021 | 4 | 4 |
| 2022 | 4 | 7 |
| 2023 | 4 | 2 |
| 2024 | 3 | 6 |
| 2025 | 3 | 5 |
| 2026 | 3 | 5 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Heat dissipation in semiconductor devices28 Jul 2026US 12,696,763 B2Taiwan Semiconductor Manufacturing Company.Ltd
- IC package with dummy die heat spreader23 Jun 2026US 12,666,963 B2Samsung Electronics Co., Ltd.
- Packaging structure having semiconductor chips and encapsulation layers and formation method thereof24 Feb 2026US 12,564,083 B2Nantong Tongfu Microelectronics Co., Ltd
- Metal nanoparticles in an amorphous bonding layer between a device substrate and carrier substrate2 Dec 2025US 12,489,082 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Anisotropic conductive film with carbon-based conductive regions having void space and related semiconductor device assemblies and methods15 Jul 2025US 12,362,311 B2Micron Technology, Inc.
- Heat dissipation in semiconductor devices8 Oct 2026US 2026/0314410 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Methods and apparatus for substrate processing4 Jun 2026US 2026/0157176 A1APPLIED Materials.Inc.
- Wafer bonding method and semiconductor structure manufactured using the same9 Apr 2026US 2026/0101684 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor package and method of manufacturing semiconductor package9 Apr 2026US 2026/0101749 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Thermally conductive substrate bonding interface29 Jan 2026US 2026/0027805 A1Tokyo Electron Limited
Most cited
By later US patents
- Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer27US 9,142,532 B2Bondtech Co., Ltd. · 2015
- Integrated circuit package and method12US 11,024,605 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2021
- Integrated circuit package and method12US 11,502,062 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2022
- Method for bonding metallic contact areas with solution of a sacrificial layer applied on one of the contact areas9US 9,640,510 B2EV Group E. Thallner GmbH · 2017
- Methods for forming semiconductor device packages8US 9,202,714 B2Micron Technology, Inc. · 2015