IC package with dummy die heat spreader

A semiconductor package, comprising:

• a substrate;
• a semiconductor chip on the substrate;
• an interposer substrate between the substrate and the semiconductor chip;
• a chip stack on the interposer substrate;
• a dummy chip on the semiconductor chip;
• and
• a first protection layer between the semiconductor chip and the dummy chip,
• wherein the chip stack is spaced apart from the semiconductor chip in a first direction parallel to a top surface of the semiconductor chip,
• wherein the dummy chip comprises:
• a semiconductor substrate comprises a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the semiconductor chip;
• a second protection layer on the first surface;
• and
• a penetration electrode penetrating the semiconductor substrate and the second protection layer,
• wherein the penetration electrode is spaced apart from the semiconductor chip in a second direction perpendicular to the top surface of the semiconductor chip, and
• wherein the first protection layer is in contact with the second protection layer.

A semiconductor package, comprising:

• a first sub-package;
• and
• a second sub-package on the first sub-package,
• wherein the first sub-package comprises:
• a lower redistribution substrate;
• a first semiconductor chip on the lower redistribution substrate;
• a dummy chip on the first semiconductor chip;
• and
• a first protection layer between the first semiconductor chip and the dummy chip,
• wherein the dummy chip comprises:
• a semiconductor substrate comprising a first surface and a second surface, opposite to the first surface, the first surface being closer than the second surface to the first semiconductor chip;
• a second protection layer on the first surface;
• and
• a penetration electrode penetrating the semiconductor substrate and the second protection layer,
• wherein the penetration electrode is spaced apart from the first semiconductor chip in a first direction perpendicular to a top surface of the first semiconductor chip,
• wherein the first protection layer is in contact with the second protection layer, and
• wherein the second sub-package comprises:
• an upper redistribution substrate;
• a second semiconductor chip on the upper redistribution substrate;
• and
• an upper substrate between the upper redistribution substrate and the second semiconductor chip.