H10W 72/01221
Using local deposition
Official title: {using local deposition}
H10W72/01221 (Using local deposition) appears on 3,710 US grants and 3,862 published applications in this corpus.
Search patents in H10W- Granted patents
- 3,710
- Published applications
- 3,862
- Assignees
- 680
- Inventors
- 5,192
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 4 | 0 |
| 1990 | 4 | 0 |
| 1991 | 8 | 0 |
| 1992 | 13 | 0 |
| 1993 | 12 | 0 |
| 1994 | 15 | 0 |
| 1995 | 7 | 0 |
| 1996 | 24 | 0 |
| 1997 | 25 | 0 |
| 1998 | 42 | 0 |
| 1999 | 72 | 0 |
| 2000 | 71 | 0 |
| 2001 | 110 | 64 |
| 2002 | 107 | 146 |
| 2003 | 118 | 123 |
| 2004 | 109 | 126 |
| 2005 | 99 | 140 |
| 2006 | 107 | 118 |
| 2007 | 80 | 164 |
| 2008 | 76 | 168 |
| 2009 | 102 | 172 |
| 2010 | 128 | 155 |
| 2011 | 134 | 159 |
| 2012 | 141 | 168 |
| 2013 | 159 | 177 |
| 2014 | 137 | 204 |
| 2015 | 176 | 254 |
| 2016 | 246 | 223 |
| 2017 | 241 | 214 |
| 2018 | 215 | 203 |
| 2019 | 187 | 192 |
| 2020 | 174 | 184 |
| 2021 | 139 | 172 |
| 2022 | 136 | 113 |
| 2023 | 109 | 66 |
| 2024 | 97 | 71 |
| 2025 | 64 | 56 |
| 2026 | 17 | 30 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Repair of solder bumps29 Sep 2026US 12,746,613 B2Orbotech Ltd.
- Package structure and method for fabricating the same1 Sep 2026US 12,727,477 B2Wistron Neweb Corp.
- Sintered metal flip chip joints18 Aug 2026US 12,713,938 B2Texas Instruments Incorporated
- Semiconductor package and manufacturing method therefor11 Aug 2026US 12,708,031 B2LG Innotek Co., Ltd.
- Die attachment structure and method8 Oct 2026US 2026/0314435 A1NXP USA, Inc.
- Semiconductor Device and Method of Forming Stacked Encapsulated Conductive Pillar Layers as Vertical Interconnect Structure17 Sep 2026US 2026/0282965 A1STATS ChipPAC Pte. Ltd.
- Laser printing method for microbumps in packaging three-dimensional integrated circuit17 Sep 2026US 2026/0282988 A1Shanghai Jiao Tong University
- Method for forming copper pillars by thick film screen printing10 Sep 2026US 2026/0271632 A1
- Method for forming copper pillars by copper paste screen printing10 Sep 2026US 2026/0271763 A1
Most cited
By later US patents
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Embedded wafer-level bonding approaches616US 8,361,842 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2013
- Sockets for electronic components and methods of connecting to electronic components453US 5,772,451 AForm Factor, Inc. · 1998
- Method of manufacturing electrical contacts, using a sacrificial member437US 5,476,211 AForm Factor, Inc. · 1995
- Saw-singulated leadless plastic chip carrier427US 6,229,200 B1ASAT Ltd. · 2001