H10W 46/603
Formed on wafers or substrates before dicing and remaining on chips after
Official title: {Formed on wafers or substrates before dicing and remaining on chips after dicing}
H10W46/603 (Formed on wafers or substrates before dicing and remaining on chips after) appears on 429 US grants and 498 published applications in this corpus.
Search patents in H10W- Granted patents
- 429
- Published applications
- 498
- Assignees
- 198
- Inventors
- 893
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 6 | 0 |
| 1995 | 2 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 3 | 0 |
| 1999 | 10 | 0 |
| 2000 | 10 | 0 |
| 2001 | 12 | 7 |
| 2002 | 14 | 13 |
| 2003 | 13 | 19 |
| 2004 | 19 | 38 |
| 2005 | 16 | 31 |
| 2006 | 28 | 42 |
| 2007 | 20 | 31 |
| 2008 | 17 | 26 |
| 2009 | 14 | 41 |
| 2010 | 28 | 23 |
| 2011 | 32 | 32 |
| 2012 | 24 | 19 |
| 2013 | 21 | 11 |
| 2014 | 27 | 22 |
| 2015 | 18 | 13 |
| 2016 | 8 | 12 |
| 2017 | 12 | 12 |
| 2018 | 9 | 6 |
| 2019 | 7 | 10 |
| 2020 | 11 | 8 |
| 2021 | 6 | 10 |
| 2022 | 6 | 6 |
| 2023 | 5 | 15 |
| 2024 | 6 | 19 |
| 2025 | 11 | 16 |
| 2026 | 8 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- First chip and wafer bonding method and chip stacking structure18 Aug 2026US 12,713,934 B2Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
- Semiconductor device and semiconductor chip4 Aug 2026US 12,702,017 B2Samsung Electronics Co., Ltd.
- Electronic package having a chip with a trench in the surface30 Jun 2026US 12,672,553 B2Siliconware Precision Industries Co., Ltd.
- Semiconductor package and method of fabricating the same12 May 2026US 12,628,658 B2Samsung Electronics Co., Ltd.
- Integrated passive device dies and methods of forming and placement of the same14 Apr 2026US 12,604,765 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming alignment keys of semiconductor structure and semiconductor structure having alignment keys13 Aug 2026US 2026/0239996 A1United Microelectronics Corp.
- Backside markings and marking grooves for wafer-level chip scale packaging dice6 Aug 2026US 2026/0231710 A1Cirrus Logic International Semiconductor Ltd.
- Integrated passive device dies and methods of forming and placement of the same23 Jul 2026US 2026/0215342 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Die Labelling for Semiconductor Die9 Jul 2026US 2026/0198331 A1Wolfspeed, Inc.
- Precise Wafer Alignment21 May 2026US 2026/0140165 A1Intelligent Memory Limited
Most cited
By later US patents
- Alignment of MTJ stack to conductive lines in the absence of topography273US 7,223,612 B2Infineon Technologies AG · 2007
- Procedure for arranging chips of a first substrate on a second substrate175US 7,772,039 B2Infineon Technologies AG · 2010
- Direct application of unpackaged integrated circuit to flexible printed circuit155US 5,261,593 ASheldahl, Inc. · 1993
- Method and system for identifying defects in a semiconductor144US 6,292,582 B12001
- Microlabelling system and process for making microlabels131US 5,118,369 AColorCode Unlimited Corporation · 1992