First chip and wafer bonding method and chip stacking structure

A method of bonding first die(s) to a wafer, comprising:

• providing a first layer of first die(s), the first layer of first die(s) including N first die(s) each comprising a first substrate, a first dielectric layer on the first substrate and a first metal layer embedded in the first dielectric layer, where N is an integer≥1;
• providing the wafer, which comprises a second metal layer;
• bonding the N first die(s) to the wafer, wherein when N≥2, the N first dies are spaced apart on the wafer;
• forming an insulating layer and a hole, wherein when N=1, the insulating layer covers a top surface of the single first die and the wafer around the single first die;
• when N≥2, the insulating layer covers top surfaces of the N first dies and fills gap(s) between the N first dies on the wafer;
• N=1 or N≥2, and a top surface of the insulating layer on the wafer is higher than the top surface(s) of the first die(s);
• and the hole comprises a first hole, which extends through the insulating layer and a partial thickness of the wafer and exposes the second metal layer;
• and
• forming an interconnect structure, which is filled in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, wherein the interconnect structure is in direct electrical contact with the first metal layer or the second metal layer.