Semiconductor package and method of fabricating the same

A semiconductor package comprising:

• a semiconductor package substrate;
• a first semiconductor chip on the semiconductor package substrate;
• a plurality of second semiconductor chips stacked on the first semiconductor chip;
• a plurality of first chip connection bumps between the semiconductor package substrate and the first semiconductor chip;
• a plurality of second chip connection bumps between the first semiconductor chip and a bottommost second semiconductor chip of the plurality of second semiconductor chips or between two adjacent second semiconductor chips of the plurality of second semiconductor chips;
• a protective insulating layer between the semiconductor package substrate and the first semiconductor chip, the first semiconductor chip and the bottommost second semiconductor chip, or between the two adjacent second semiconductor chips, the protective insulating layer contacting the plurality of first chip connection bumps or the plurality of second chip connection bumps;
• and
• a first dummy conductive structure at a bottom surface of each second semiconductor chip of the plurality of second semiconductor chips,
• wherein when viewed in a plan view, the first dummy conductive structure surrounds an outer boundary of a region where the plurality of second chip connection bumps are disposed,
• wherein the bottom surface of each second semiconductor chip of the plurality of second semiconductor chips faces the first semiconductor chip,
• wherein the first dummy conductive structure includes a plurality of first dummy patterns arranged along an edge of each second semiconductor chip of the plurality of second semiconductor chips, and
• wherein the plurality of first dummy patterns are separated from each other-,
• wherein, when viewed in the plan view, each of the plurality of second semiconductor chips includes an outer space surrounding the outer boundary of the region where the plurality of second chip connection bumps,
• wherein the outer space includes a first region adjacent to a center of the edge of each second semiconductor chip of the plurality of second semiconductor chips, and a second region adjacent to a vertex of each of the plurality of second semiconductor chips, and
• wherein a horizontal distance between two adjacent first dummy patterns of the plurality of first dummy patterns increases toward the second region.

A method of fabricating a semiconductor package, the method comprising:

• arranging a plurality of chip connection bumps on a bottom surface of a second semiconductor chip, the second semiconductor chip including a top surface and the bottom surface;
• forming a dummy conductive structure at the bottom surface of the second semiconductor chip, wherein the dummy conductive structure includes a plurality of dummy patterns separated from each other;
• forming a protective insulating layer on the bottom surface of the second semiconductor chip, the protective insulating layer adhering to the plurality of chip connection bumps;
• stacking the second semiconductor chip on a first semiconductor chip, the first semiconductor chip facing the bottom surface of the second semiconductor chip;
• and
• pre-curing a portion of the protective insulating layer, the portion of the protective insulating layer overlapping the plurality of dummy patterns in a vertical direction,
• wherein the bottom surface of the second semiconductor chip includes, when viewed in a plan view:
• an inner bottom surface that the plurality of chip connection bumps contact, and
• an outer bottom surface surrounding the inner bottom surface,
• wherein the dummy conductive structure is at the outer bottom surface of the bottom surface of the second semiconductor chip, and
• wherein the plurality of dummy patterns are arranged along an edge of the bottom surface of the second semiconductor chip.