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US 12,702,017 B2Granted
Semiconductor device and semiconductor chip
AssigneeSamsung Electronics Co., Ltd.
InventorsJimin Choi, Joongwon Shin, Sungyun Woo, Yeonjin Lee, Jongmin Lee, Sehyun Hwang
Life of this patent
Estimating the term…
Abstract
A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.
Claims20
A semiconductor device, comprising:
- a plurality of chip regions on a substrate, each chip region of the plurality of chip regions including at least one circuit pattern for at least one integrated circuit device;
- at least one scribe lane surrounding each chip region of the plurality of chip regions on the substrate;
- a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions when viewed from a vertical direction;
- and
- a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane when viewed from the vertical direction, wherein
- the plurality of chip regions are separated from each other along the at least one scribe lane.
3 more elements
A semiconductor device, comprising:
- a plurality of integrated circuit devices;
- a shot group of a substrate, the shot group including a plurality of chip regions, the shot group having an area covered by a single shot of a photolithography process;
- at least one scribe lane on the substrate, the at least one scribe lane surrounding the plurality of chip regions;
- a first region included in each chip region of the plurality of chip regions, the first region including at least one of a plurality of first align key patterns and a plurality of first test element group patterns when viewed from a vertical direction;
- and
- a main region included in each chip region of the plurality of chip regions, the main region including the plurality of integrated circuit devices,
- the plurality of first align key patterns included in the plurality of chip regions of the shot group include a plurality of align key patterns used in different exposure processes, and the plurality of first test element group patterns included in the plurality of chip regions of the shot group include a plurality of patterns configured to provide a plurality of different tests of the plurality of integrated circuit devices, wherein the plurality of chip regions are separated from each other along the at least one scribe lane.
4 more elements
A semiconductor chip, comprising:
- a plurality of integrated circuit devices;
- a chip region;
- at least one scribe lane surrounding the chip region;
- a first region included in the chip region, the first region including a plurality of first align key patterns and a plurality of first test element group patterns when viewed from a vertical direction;
- and
- a main region included in the chip region, the main region including the plurality of integrated circuit devices, wherein the chip region is separated from other chip regions along the at least one scribe lane.
3 more elements
Dependencies are inferred from the claim text.