Method for forming alignment keys of semiconductor structure and semiconductor structure having alignment keys

A method for forming alignment keys of a semiconductor structure, the method comprising steps of:

• providing a substrate, wherein at least one low voltage region, at least one medium voltage region, at least one high voltage region and at least one alignment mark region are defined on the substrate, and the at least one high voltage region is adjacent to the at least one alignment mark region;
• forming an oxide pad layer on the substrate;
• forming a passivation layer on the oxide pad layer;
• forming a first patterned photoresist layer on the passivation layer, wherein the first patterned photoresist layer has a plurality of first patterned openings, the first patterned openings correspond to and expose the at least one medium voltage region and the at least one alignment mark region;
• using the first patterned photoresist layer as a mask to remove a part of the passivation layer and a part of the oxide pad layer exposed through the first patterned openings, so as to form a plurality of grooves on the stacked oxide pad layer and passivation layer, wherein the grooves correspond to the at least one medium voltage region and the at least one alignment mark region, and a part of the substrate is exposed through the grooves;
• removing the first patterned photoresist layer;
• performing an oxidation process on the exposed part of the substrate in the grooves to form a plurality of oxide portions on a part of the substrate, wherein the oxide portions correspond to the at least one medium voltage region and the at least one alignment mark region, and each of the oxide portions is formed in the respective groove and extends into a first depth of the substrate;
• forming a second patterned photoresist layer, wherein the second patterned photoresist layer has a plurality of second patterned openings, the second patterned openings correspond to the at least one low voltage region and the at least one medium voltage region, and the second patterned photoresist layer covers the oxide portions in the at least one alignment mark region and a part of the passivation layer in the at least one high voltage region and exposes the oxide portions in the at least one medium voltage region and a part of the passivation layer in the at least one low voltage region;
• using the second patterned photoresist layer as a mask to perform a first ion implantation on the at least one medium voltage region and the at least one low voltage region through the second patterned openings;
• removing the second patterned photoresist layer;
• performing a cleaning process to remove a part of the oxide portions located in the grooves;
• forming a third patterned photoresist layer, wherein the third patterned photoresist layer has a plurality of third patterned openings, the third patterned openings correspond to the at least one high voltage region and the at least one alignment mark region, the third patterned photoresist layer covers the oxide portions in the at least one medium voltage region and a part of the passivation layer in the at least one low voltage region and exposes the oxide portions in the at least one alignment mark region and a part of the passivation layer in the at least one high voltage region;
• using the third patterned photoresist layer as a mask to perform a second ion implantation on the at least one high voltage region and the at least one alignment mark region through the third patterned openings;
• using the third patterned photoresist layer as a mask to perform an etching process on the at least one high voltage region and the at least one alignment mark region, so as to remove the oxide portions and a part of the substrate in the at least one alignment mark region and remove at least a part of the passivation layer in the at least one high voltage region, wherein a second trench having a second depth is formed in the at least one alignment mark region of the substrate;
• removing the third patterned photoresist layer;
• removing the passivation layer;
• and
• removing the oxide pad layer and the oxide portions, wherein a first trench having the first depth is formed in the at least one medium voltage region after the oxide portions in the at least one medium voltage region are removed, and the first depth is less than the second depth.