H10W 20/425
Barrier, adhesion or liner layers
Official title: {Barrier, adhesion or liner layers}
H10W20/425 (Barrier, adhesion or liner layers) appears on 6,851 US grants and 7,371 published applications in this corpus.
Search patents in H10W- Granted patents
- 6,851
- Published applications
- 7,371
- Assignees
- 691
- Inventors
- 8,603
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 3 | 0 |
| 1978 | 6 | 0 |
| 1979 | 6 | 0 |
| 1980 | 3 | 0 |
| 1981 | 4 | 0 |
| 1982 | 3 | 0 |
| 1983 | 2 | 0 |
| 1984 | 4 | 0 |
| 1985 | 6 | 0 |
| 1986 | 4 | 0 |
| 1987 | 7 | 0 |
| 1988 | 5 | 0 |
| 1989 | 7 | 0 |
| 1990 | 24 | 0 |
| 1991 | 26 | 0 |
| 1992 | 23 | 0 |
| 1993 | 22 | 0 |
| 1994 | 41 | 0 |
| 1995 | 42 | 0 |
| 1996 | 46 | 0 |
| 1997 | 58 | 0 |
| 1998 | 70 | 0 |
| 1999 | 93 | 0 |
| 2000 | 122 | 0 |
| 2001 | 148 | 63 |
| 2002 | 196 | 203 |
| 2003 | 151 | 161 |
| 2004 | 163 | 194 |
| 2005 | 116 | 216 |
| 2006 | 137 | 197 |
| 2007 | 149 | 203 |
| 2008 | 125 | 259 |
| 2009 | 128 | 254 |
| 2010 | 204 | 237 |
| 2011 | 213 | 185 |
| 2012 | 182 | 230 |
| 2013 | 195 | 213 |
| 2014 | 254 | 359 |
| 2015 | 273 | 411 |
| 2016 | 402 | 457 |
| 2017 | 494 | 438 |
| 2018 | 430 | 421 |
| 2019 | 397 | 372 |
| 2020 | 347 | 386 |
| 2021 | 303 | 306 |
| 2022 | 249 | 362 |
| 2023 | 249 | 401 |
| 2024 | 251 | 359 |
| 2025 | 277 | 303 |
| 2026 | 189 | 181 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device6 Oct 2026US 12,757,453 B2Fuji Electric Co., Ltd.
- Semiconductor device and method of manufacturing the same6 Oct 2026US 12,757,688 B2SK hynix Inc.
- Asymmetric skip-level via structure6 Oct 2026US 12,757,702 B2International Business Machines Corporation
- Semiconductor substrate comprising a through-substrate-via and method for producing thereof6 Oct 2026US 12,757,705 B2ams-OSRAM AG
- Barrier layers for interconnects in bonded wafers6 Oct 2026US 12,757,721 B2United Microelectronics Corp.
- Interconnect structure and method of forming same8 Oct 2026US 2026/0306859 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device including a self-formed barrier metal layer8 Oct 2026US 2026/0314351 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Low resistance interconnect features and method for manufacturing the same8 Oct 2026US 2026/0314352 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Conductive structures and methods of forming the same8 Oct 2026US 2026/0314355 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method to improve interconnect coefficient of thermal expansion8 Oct 2026US 2026/0314357 A1APPLIED Materials.Inc.
Most cited
By later US patents
- Dummy structure for chip-on-wafer-on-substrate961US 9,425,126 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Production of elemental thin films using a boron-containing reducing agent809US 6,475,276 B1ASM Microchemistry Oy · 2002
- Plated copper interconnect structure621US 5,969,422 AAdvanced Micro Devices, Inc. · 1999
- Structures and methods for integration of ultralow-k dielectrics with improved reliability554US 7,088,003 B2International Business Machines Corporation · 2006
- Method of doping metal layers for electromigration resistance541US 5,681,779 ALSI Logic Corporation · 1997