Semiconductor substrate comprising a through-substrate-via and method for producing thereof

A semiconductor device, comprising:

• a substrate with a rear surface and a main surface,
• an intermetal dielectric arranged on the main surface of substrate,
• a metal layer embedded in the intermetal dielectric, the metal layer comprising a top barrier layer, wherein the top barrier layer is arranged at a side of the metal layer facing away from the substrate, and
• a through-substrate-via, TSV, reaching from the rear surface of the substrate to the top barrier layer of the metal layer, the TSV comprising a metallization being configured to electrically contact the metal layer from the rear surface of the substrate, wherein
• the TSV comprises a via hole, the via hole penetrating the substrate and the intermetal dielectric between the substrate and the metal layer, the via hole further penetrating the metal layer up to the top barrier layer,
• wherein the metallization of the TSV comprises a sidewall portion covering a sidewall of the TSV and a base portion covering the top barrier layer of the metal layer, wherein, at the metal layer, the sidewall portion of the metallization tapers conically to the base portion of the metallization, and
• wherein the metal layer, apart from the top barrier layer, forms a ring around the TSV, such that a side surface of the ring is in direct contact with the metallization of the TSV forming a contact area for establishing an electrical interconnection.

A semiconductor device, comprising:

• a substrate with a rear surface and a main surface,
• an intermetal dielectric arranged on the main surface of substrate,
• a metal layer embedded in the intermetal dielectric, the metal layer comprising a top barrier layer, wherein the top barrier layer is arranged at a side of the metal layer facing away from the substrate,
• a through-substrate-via, TSV, reaching from the rear surface of the substrate to the top barrier layer of the metal layer, the TSV comprising a metallization being configured to electrically contact the metal layer from the rear surface of the substrate, wherein
• the TSV comprises a via hole, the via hole penetrating the substrate and the intermetal dielectric between the substrate and the metal layer, the via hole further penetrating the metal layer up to the top barrier layer,
• wherein the metallization of the TSV comprises a sidewall portion covering a sidewall of the TSV and a base portion covering the top barrier layer of the metal layer, wherein, at the metal layer, the sidewall portion of the metallization tapers conically to the base portion of the metallization,
• at least one further metal layer embedded in the intermetal dielectric, the further metal layer comprising a further top barrier layer, wherein the further top barrier layer is arranged at a side of the further metal layer facing away from the substrate, and wherein the further metal layer has a larger distance from the substrate than the metal layer, and
• at least one further TSV reaching from the rear surface of the substrate to the further top barrier layer of the further metal layer, the further TSV comprising a further metallization being configured to electrically contact the further metal layer from the rear surface of the substrate.