Back to results
US 2026/0314351 A1Published application
Semiconductor device including a self-formed barrier metal layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Kang FU, Hsien-Chang WU, Ming-Han LEE, Shau-Lin SHUE
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.
Claims20
A method for manufacturing a semiconductor device, comprising:
- patterning an interconnect layer that is disposed over a substrate to form a recess in the interconnect layer;
- filling a metal material into the recess, the metal material including an alloy;
- performing a planarization treatment to remove an excess portion of the metal material, so as to form a metal line and a metal oxide layer in the recess, the metal line including a remaining portion of the metal material and a barrier metal layer disposed on the remaining portion of the metal material, the metal oxide layer being disposed on the barrier metal layer opposite to the remaining portion of the metal material;
- patterning, by using the metal oxide layer as an etch stop layer, a dielectric layer that is disposed over the interconnect layer, so as to form at least one via opening and at least one trench in the dielectric layer, a bottom surface of the metal oxide layer being lower than a bottom surface of the dielectric layer;
- and
- filling a conductive metal material into the at least one via opening and the at least one trench to form at least one via contact and at least one conductive line in the dielectric layer, the at least one via contact being electrically connected to the metal line.
3 more elements
A method for manufacturing a semiconductor device, comprising:
- patterning an interconnect layer that is disposed over a substrate to form a first recess in the interconnect layer;
- filling a first metal material into the first recess, the first metal material including an alloy which is a mixture of two metal elements;
- depositing a second metal material on the first metal material, the second metal material being different from the first metal material;
- performing a planarization treatment to remove an excess portion of the second metal material and an excess portion of the first metal material, so as to form a first metal line and a metal oxide layer in the first recess, the first metal line including a remaining portion of the first metal material and a barrier metal layer disposed on the remaining portion of the first metal material, the metal oxide layer being disposed on the barrier metal layer opposite to the remaining portion of the first metal material;
- patterning, by using the metal oxide layer as an etch stop layer, a dielectric layer that is disposed over the interconnect layer, so as to form at least one via opening and at least one trench in the dielectric layer;
- and
- filling a conductive metal material into the at least one via opening and the at least one trench to form at least one via contact and at least one conductive line in the dielectric layer, the at least one via contact being electrically connected to the first metal line.
4 more elements
A method for manufacturing a semiconductor device, comprising:
- patterning an interconnect layer that is disposed over a substrate to form a recess in the interconnect layer;
- filling a metal material into the recess, the metal material including an alloy which is a mixture of two metal elements;
- performing a first planarization treatment to remove an excess portion of the metal material so as to form a metal line and a metal oxide layer in the recess, the metal line including a barrier metal layer disposed on a remaining portion of the metal material, the metal oxide layer being disposed on the barrier metal layer opposite to the remaining portion of the metal material;
- performing a second planarization treatment to remove the metal oxide layer;
- forming a dielectric layer on the interconnect layer opposite to the substrate;
- patterning the dielectric layer so as to form at least one via opening and at least one trench in the dielectric layer;
- and
- filling a conductive metal material into the at least one via opening and the at least one trench to form at least one via contact and at least one conductive line in the dielectric layer, the at least one via contact being electrically connected to the metal line.
5 more elements
Dependencies are inferred from the claim text.