Method to improve interconnect coefficient of thermal expansion
AssigneeApplied Materials, Inc.
InventorsTyler Sherwood, Raghav Sreenivasan
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Abstract
The present technology includes semiconductor processing methods and devices with improved expansion of the bulk material in substrate features. Methods include cleaning a substrate that is formed from silicon oxide and that defines one or more features and that includes a liner that extends across the silicon oxide and within one or more features and a copper-containing layer deposited on the liner and extending within the one or more features. Methods include depositing a second metal over the substrate, where the second metal has a coefficient of thermal expansion of greater than or about 17. Methods also include diffusing the second metal into the copper containing layer to form a copper alloy.
Claims20
A semiconductor device, comprising:
- a silicon oxide substrate defining two or more features, each feature comprising a first side, a second side, and a bottom;
- a liner extending across the silicon oxide substrate and within the two or more features;
- and
- a copper-alloy layer deposited on the liner and extending within the two or more features, wherein the copper-alloy layer has a coefficient of thermal expansion of greater than or about 17.
Dependencies are inferred from the claim text.