H10W 20/021
Of interconnections within wafers or substrates
Official title: {of interconnections within wafers or substrates}
H10W20/021 (Of interconnections within wafers or substrates) appears on 8,734 US grants and 10,544 published applications in this corpus.
Search patents in H10W- Granted patents
- 8,734
- Published applications
- 10,544
- Assignees
- 1,037
- Inventors
- 11,106
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 6 | 0 |
| 1977 | 11 | 0 |
| 1978 | 17 | 0 |
| 1979 | 7 | 0 |
| 1980 | 7 | 0 |
| 1981 | 10 | 0 |
| 1982 | 7 | 0 |
| 1983 | 11 | 0 |
| 1984 | 14 | 0 |
| 1985 | 16 | 0 |
| 1986 | 13 | 0 |
| 1987 | 15 | 0 |
| 1988 | 18 | 0 |
| 1989 | 27 | 0 |
| 1990 | 27 | 0 |
| 1991 | 22 | 0 |
| 1992 | 22 | 0 |
| 1993 | 22 | 0 |
| 1994 | 31 | 0 |
| 1995 | 19 | 0 |
| 1996 | 20 | 0 |
| 1997 | 18 | 0 |
| 1998 | 21 | 0 |
| 1999 | 34 | 0 |
| 2000 | 40 | 0 |
| 2001 | 45 | 18 |
| 2002 | 76 | 91 |
| 2003 | 84 | 95 |
| 2004 | 86 | 147 |
| 2005 | 101 | 174 |
| 2006 | 136 | 234 |
| 2007 | 98 | 228 |
| 2008 | 120 | 294 |
| 2009 | 170 | 292 |
| 2010 | 249 | 380 |
| 2011 | 318 | 478 |
| 2012 | 345 | 545 |
| 2013 | 502 | 524 |
| 2014 | 534 | 560 |
| 2015 | 519 | 616 |
| 2016 | 600 | 459 |
| 2017 | 512 | 445 |
| 2018 | 453 | 429 |
| 2019 | 426 | 421 |
| 2020 | 418 | 479 |
| 2021 | 426 | 533 |
| 2022 | 382 | 624 |
| 2023 | 457 | 702 |
| 2024 | 481 | 724 |
| 2025 | 475 | 645 |
| 2026 | 266 | 407 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Semiconductor substrate comprising a through-substrate-via and method for producing thereof6 Oct 2026US 12,757,705 B2ams-OSRAM AG
- Semiconductor device with polymer liner and method for fabricating the same6 Oct 2026US 12,757,707 B2Nanya Technology Corporation
- Semiconductor device having a through contact connected to a buried pattern and penetrating a field insulation film and an etch stop layer6 Oct 2026US 12,757,719 B2Samsung Electronics Co., Ltd.
- Barrier layers for interconnects in bonded wafers6 Oct 2026US 12,757,721 B2United Microelectronics Corp.
- Semiconductor structure and alignment method thereof6 Oct 2026US 12,757,744 B2United Microelectronics Corp.
- Interconnect structure and method of forming same8 Oct 2026US 2026/0306859 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Air liner for through substrate via8 Oct 2026US 2026/0313968 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming through wafer via8 Oct 2026US 2026/0314349 A1Skyworks Solutions, Inc.
- Package structure and method for fabricating the same8 Oct 2026US 2026/0314354 A1National Yang Ming.Chiao Tung University
- Via structure and method for forming the same8 Oct 2026US 2026/0314367 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Structure and method for 3D IC package971US 8,993,380 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Dummy structure for chip-on-wafer-on-substrate961US 9,425,126 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Package of integrated circuits and vertical integration749US 6,322,903 B1Tru-Si Technologies, Inc. · 2001