H10D 64/514
Characterised by the insulating layers
Official title: {characterised by the insulating layers}
H10D64/514 (Characterised by the insulating layers) appears on 5,288 US grants and 6,058 published applications in this corpus.
Search patents in H10D- Granted patents
- 5,288
- Published applications
- 6,058
- Assignees
- 733
- Inventors
- 7,008
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 8 | 0 |
| 1982 | 2 | 0 |
| 1983 | 4 | 0 |
| 1984 | 1 | 0 |
| 1985 | 4 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 3 | 0 |
| 1989 | 8 | 0 |
| 1990 | 9 | 0 |
| 1991 | 12 | 0 |
| 1992 | 13 | 0 |
| 1993 | 20 | 0 |
| 1994 | 27 | 0 |
| 1995 | 28 | 0 |
| 1996 | 23 | 0 |
| 1997 | 28 | 0 |
| 1998 | 36 | 0 |
| 1999 | 33 | 0 |
| 2000 | 53 | 0 |
| 2001 | 64 | 38 |
| 2002 | 62 | 96 |
| 2003 | 86 | 90 |
| 2004 | 86 | 106 |
| 2005 | 90 | 119 |
| 2006 | 79 | 158 |
| 2007 | 84 | 138 |
| 2008 | 98 | 162 |
| 2009 | 109 | 174 |
| 2010 | 137 | 180 |
| 2011 | 156 | 169 |
| 2012 | 166 | 219 |
| 2013 | 197 | 247 |
| 2014 | 264 | 342 |
| 2015 | 361 | 432 |
| 2016 | 391 | 428 |
| 2017 | 397 | 338 |
| 2018 | 328 | 322 |
| 2019 | 329 | 329 |
| 2020 | 277 | 305 |
| 2021 | 251 | 281 |
| 2022 | 229 | 306 |
| 2023 | 208 | 279 |
| 2024 | 203 | 246 |
| 2025 | 214 | 305 |
| 2026 | 101 | 249 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Manufacturing method of semiconductor structure and semiconductor structure29 Sep 2026US 12,751,069 B2Changxin Jidian (Beijing) Memory Technologies Co., Ltd.
- Split gate trench device29 Sep 2026US 12,751,071 B2Excelliance MOS Corporation
- Semiconductor device29 Sep 2026US 12,751,072 B2United Microelectronics Corp.
- Semiconductor memory device including buried gate pattern15 Sep 2026US 12,740,048 B2Samsung Electronics Co., Ltd.
- Semiconductor device structure having gate dielectric layers with different dielectric compositions and method of forming the same15 Sep 2026US 12,740,136 B2Mediatek Inc.
- Controlled doping in a gate dielectric layer8 Oct 2026US 2026/0313932 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Nitride semiconductor device and manufacturing method of nitride semiconductor device8 Oct 2026US 2026/0313996 A1Wavetek Microelectronics Corporation
- Semiconductor device and manufacturing method thereof8 Oct 2026US 2026/0314027 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Stacked fet with dielectric spacer between gate metal and source/drain contact8 Oct 2026US 2026/0314047 A1International Business Machines Corporation
- Integrated circuit structures having both spine-fet and gaa architectures1 Oct 2026US 2026/0304728 A1Intel Corporation
Most cited
By later US patents
- Wrap-around contact550US 9,443,769 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Power semiconductor devices having improved high frequency switching and breakdown characteristics442US 5,998,833 ANorth Carolina State University · 1999
- Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance374US 5,637,898 ANorth Carolina State University · 1997
- Monolithic three dimensional array of charge storage devices containing a planarized surface361US 6,881,994 B2Matrix Semiconductor, Inc. · 2005
- Semiconductor devices exhibiting minimum on-resistance320US 4,941,026 AGeneral Electric Company · 1990