Integrated circuit structures having both spine-fet and gaa architectures

Abstract

Integrated circuit structures having both spine-FET and gate-all-around (GAA) architectures are described. In an example, a structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first gate electrode is around the first vertical stack of nanowires. A second vertical stack of nanowires is laterally spaced apart from the first vertical stack of nanowires, the second vertical stack of nanowires free from a dielectric backbone. A second gate electrode is around the second vertical stack of nanowires.

Dependencies are inferred from the claim text.