Monolithic three dimensional array of charge storage devices containing a planarized surface
AssigneeMatrix Semiconductor, Inc.
InventorsThomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
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Abstract
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
Claims52
A monolithic three dimensional array comprising a plurality of device levels containing charge storage devices disposed above a substrate, the array comprising:
- a first layer of transition metal-crystallized silicon disposed above the substrate;
- a p-n junction disposed in said first layer;
- and
- a local charge storage film disposed adjacent to said first layer;
- wherein the p-n junction comprises a junction between a source region and a channel or a drain region and a channel.
A semiconductor device comprising:
- a monolithic three dimensional array of charge storage devices formed in an amorphous or polycrystalline semiconductor layer over a monocrystalline semiconductor substrate;
- and
- driver circuitry formed in the substrate at least in part under the array, within the array or above the array.
A semiconductor monolithic three dimensional array of polycrystalline or amorphous charge storage devices comprising a plurality of device levels, wherein at least one surface between two successive device levels is substantially planar.
A semiconductor device comprising a monolithic three dimensional array of charge storage devices comprising a plurality of device levels, wherein at least one surface between two successive device levels has a peak to peak roughness of 4000 Angstroms or less within a stepper field.
A method of making a semiconductor device, comprising:
- forming a plurality of device levels;
- and
- planarizing at least one surface between two successive device levels by chemical mechanical polishing;
- wherein:
- the semiconductor device comprises a monolithic three dimensional array of charge storage devices comprising the plurality of device levels;
- and
- the at least one surface between the two successive device levels has a peak to peak roughness of 4000 Angstroms or less within a stepper field.
Dependencies are inferred from the claim text.