Nitride semiconductor device and manufacturing method of nitride semiconductor device

A nitride semiconductor device comprising:

• a substrate;
• a channel layer disposed on the substrate;
• a spacer layer disposed on the channel layer;
• and
• a polarization layer disposed on the spacer layer.

A manufacturing method of a nitride semiconductor device comprising:

• sequentially forming a channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, a second polarization layer and a surface cap layer on a substrate;
• partially etching the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer and the surface cap layer to form a mesa structure, wherein the mesa structure exposes the channel layer;
• forming a first passivation layer on the mesa structure, and forming a drain electrode and a source electrode on two sides of the mesa structure, wherein the drain electrode and the source electrode are located on the first passivation layer and extends from the first passivation layer to the channel layer;
• forming a second passivation layer on the first passivation layer, and partially etching the second passivation layer so that the etched second passivation layer has a through hole, wherein the through hole extends to the second spacer layer;
• forming a gate insulator layer on the second passivation layer and in the through hole;
• and
• forming a gate electrode on the gate insulator layer.

A manufacturing method of a nitride semiconductor device comprising:

• sequentially forming a channel layer, a spacer layer and a polarization layer on a substrate;
• partially etching the channel layer, the spacer layer and the polarization layer to form a mesa structure, wherein the mesa structure exposes the channel layer;
• forming a first passivation layer on the mesa structure, and forming a drain electrode and a source electrode on two sides of the mesa structure, wherein the drain electrode and the source electrode are located on the first passivation layer and extends from the first passivation layer to the channel layer;
• forming a second passivation layer on the first passivation layer, and partially etching the second passivation layer so that the etched second passivation layer has a through hole, wherein the through hole extends to the spacer layer;
• forming a gate insulator layer on the second passivation layer and in the through hole;
• and
• forming a gate electrode on the gate insulator layer.