H10D 30/795
Being in lateral device isolation regions
Official title: {being in lateral device isolation regions, e.g. STI}
H10D30/795 (Being in lateral device isolation regions) appears on 593 US grants and 695 published applications in this corpus.
Search patents in H10D- Granted patents
- 593
- Published applications
- 695
- Assignees
- 100
- Inventors
- 1,027
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2001 | 1 | 0 |
| 2002 | 0 | 1 |
| 2003 | 0 | 4 |
| 2004 | 5 | 7 |
| 2005 | 7 | 22 |
| 2006 | 9 | 26 |
| 2007 | 20 | 46 |
| 2008 | 24 | 51 |
| 2009 | 29 | 34 |
| 2010 | 35 | 22 |
| 2011 | 34 | 18 |
| 2012 | 21 | 27 |
| 2013 | 19 | 19 |
| 2014 | 30 | 20 |
| 2015 | 22 | 40 |
| 2016 | 33 | 29 |
| 2017 | 32 | 31 |
| 2018 | 33 | 31 |
| 2019 | 39 | 54 |
| 2020 | 51 | 56 |
| 2021 | 38 | 43 |
| 2022 | 30 | 20 |
| 2023 | 24 | 27 |
| 2024 | 22 | 29 |
| 2025 | 23 | 26 |
| 2026 | 12 | 12 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Multiple fin heights for effective width tuning1 Sep 2026US 12,727,191 B2International Business Machines Corporation
- Heterogeneous metal line compositions for advanced integrated circuit structure fabrication11 Aug 2026US 12,707,697 B2Intel Corporation
- Semiconductor device including diffusion break structure and method of forming semiconductor device12 May 2026US 12,628,414 B2GLOBALFOUNDRIES U. S. Inc.
- Post-replacement metal gate (RMG) gate cut for performance enhanced FinFET12 May 2026US 12,628,415 B2QUALCOMM Incorporated
- Three-dimensional (3D) field effect transistors (FETs) with gate cuts to enhance carrier mobility and related fabrication methods12 May 2026US 12,628,417 B2QUALCOMM Incorporated
- Strain engineering using fin isolation structures1 Oct 2026US 2026/0304849 A1Intel Corporation
- Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut with direct patterned trench contact and non-selective fin trim isolation2 Jul 2026US 2026/0190401 A1Intel Corporation
- Source/drain eptiaxial layer profile21 May 2026US 2026/0143757 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Fin trim plug structures with metal for imparting channel stress21 May 2026US 2026/0143758 A1Intel Corporation
- Continuous gate and fin spacer for advanced integrated circuit structure fabrication21 May 2026US 2026/0144027 A1Intel Corporation
Most cited
By later US patents
- Isolation structures for imposing stress patterns105US 6,974,981 B2International Business Machines Corporation · 2005
- Silicon device on Si:C-OI and SGOI and method of manufacture89US 7,247,534 B2International Business Machines Corporation · 2007
- Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer87US 6,703,271 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2004
- Process for making a silicon-on-insulator ledge by implanting ions from silicon source81US 6,784,076 B2Micron Technology, Inc. · 2004
- Strained-channel transistor and methods of manufacture58US 6,882,025 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2005