Strained-channel transistor and methods of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee, Chenming Hu
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Abstract
A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.
Claims66
A semiconductor device comprising:
- a region of semiconductor material;
- a first isolation trench formed in the region of semiconductor material, the first isolation trench being lined with a first material, the first material being material having a low oxygen diffusion rate, the first isolation trench further being filled with an insulating material;
- a second isolation trench formed in the region of semiconductor material, the second isolation trench not being lined with the first material, the second isolation trench further being filled with an insulating material;
- a first transistor formed adjacent the first isolation region;
- and
- a second transistor formed adjacent the second isolation region.
A semiconductor device comprising:
- a region of semiconductor material;
- a first active area disposed in a first portion of the semiconductor material:
- a first isolation region disposed adjacent the first active area, the first isolation region imposing a first type of strain on the first active area:
- a second active area disposed in a second portion of the semiconductor material:
- a second isolation region disposed adjacent the second active area, wherein the second isolation region does not impose the first type of strain on the second active area
- an n-channel transistor formed in the first active region and a p-channel transistor formed in the second active region;
- and
- a tensile stress-inducing, silicon nitride film overlying the n-channel transistor.
A semiconductor structure comprising:
- a semiconductor substrate;
- a first active region disposed in a first portion of the semiconductor substrate, the first active region located between a pair of first isolation regions, each of the first isolation regions including a silicon nitride liner;
- a second active region disposed in a second portion of the semiconductor substrate, the second active region located between a pair of second isolation regions, each of the second isolation regions including a silicon nitride liner, the silicon nitride liner of each of the second isolation regions having a characteristic that has been altered by an implantation.
A semiconductor structure comprising:
- a semiconductor substrate;
- a first active region disposed in a first portion of the semiconductor substrate, the first active region located between a pair of first isolation regions, each of the first isolation regions including a silicon nitride liner;
- a second active region disposed in a second portion of the semiconductor substrate, the second active region located between a pair of second isolation regions, each of the second isolation regions including an implanted silicon nitride liner;
- at least one n-channel transistor formed in the first active region;
- at least one p-channel transistors formed in the second active region;
- and
- a tensile stress silicon nitride film overlying the n-channel transistor.
A semiconductor structure comprising:
- a semiconductor substrate;
- a first active region with an in-plane tensile strain in a first portion of the semiconductor substrate, the first active region located between a pair of first isolation regions, wherein each of the first isolation regions include a silicon nitride liner;
- a second active region with an in-plane compressive strain in a second portion of the semiconductor substrate, the second active region located between a pair of second isolation regions, wherein the second isolation regions do not include a silicon nitride liner.
Dependencies are inferred from the claim text.