Strain engineering using fin isolation structures
AssigneeIntel Corporation
InventorsXia Li, Marko Radosavljevic, Yang Zhang, Leonard P. Guler, Charles H. Wallace, Bilal Chehab, Prashanth Aprameyan
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AssigneeIntel Corporation
InventorsXia Li, Marko Radosavljevic, Yang Zhang, Leonard P. Guler, Charles H. Wallace, Bilal Chehab, Prashanth Aprameyan
Estimating the term…
Techniques to form semiconductor devices that include one or more fin isolation structures. Different ones of the fin isolation structures are configured with diverse materials, relative to other ones of the fin isolation structures, such that they cause or otherwise impose beneficial stress (e.g., tensile or compressive) on the adjacent semiconductor devices to improve performance. The semiconductor regions of devices may be interrupted with a fin isolation structure that includes dielectric material to electrically isolate the portions of the semiconductor region on either side of the fin isolation structure. In an example, one or more first fin isolation structures are arranged between n-type transistor devices and include a dielectric material structure that imposes tensile stress on the n-type transistor devices, and one or more second fin isolation structures are arranged between p-type transistor devices and include a dielectric material structure that imposes compressive stress on the p-type transistor devices.
An integrated circuit comprising:
An electronic device, comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.