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US 12,628,417 B2Granted
Three-dimensional (3D) field effect transistors (FETs) with gate cuts to enhance carrier mobility and related fabrication methods
AssigneeQUALCOMM Incorporated
InventorsXia Li, Ming-Huei Lin, Haining Yang
Life of this patent
Estimating the term…
Abstract
A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.
Claims30
A three-dimensional (3D) field-effect transistor (FET) structure, comprising:
- at least one semiconductor slab, each comprising a channel region configured to conduct a current in a first direction;
- an insulation layer;
- a gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the insulation layer and on the at least one semiconductor slab in the channel region;
- and
- a gate cut extending through the gate material adjacent to the channel region of the at least one semiconductor slab in the second direction and extending into the insulation layer in a third direction orthogonal to the first direction and the second direction;
- wherein:
- the gate cut comprises a gate cut wedge disposed in the insulation layer, the gate cut wedge configured to cause the insulation layer to exert a first force on the channel region of the at least one semiconductor slab in the third direction.
4 more elements
A method of fabricating a three-dimensional (3D) field-effect transistor (FET) structure, the method comprising:
- forming at least one semiconductor slab, each comprising a channel region configured to conduct a current in a first direction;
- forming an insulation layer;
- forming a gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the insulation layer and on the at least one semiconductor slab in the channel region;
- and
- forming a gate cut extending through the gate material adjacent to the channel region of the at least one semiconductor slab in the second direction and extending into the insulation layer in a third direction orthogonal to the first direction and the second direction;
- wherein:
- the gate cut comprises a gate cut wedge disposed in the insulation layer, the gate cut wedge configured to cause the insulation layer to exert a first force on the channel region of the at least one semiconductor slab in the third direction.
4 more elements
A complementary metal-oxide semiconductor (CMOS) circuit structure comprising:
- at least one first semiconductor slab, each comprising:
- a first type dopant;
- a first channel region configured to conduct a first current in a first direction;
- a first source/drain region on a first side of the first channel region;
- and
- a second source/drain region on a second side of the first channel region;
- an insulation layer;
- a first gate extending in a second direction orthogonal to the first direction, the first gate comprising a gate material disposed on the insulation layer and on each of the at least one first semiconductor slab in the first channel region;
- a first gate cut extending through the first gate adjacent to the first channel region of the at least one first semiconductor slab in the second direction and extending into the insulation layer in a third direction orthogonal to the first direction and the second direction;
- at least one second semiconductor slab, each comprising:
- a second type dopant;
- a second channel region configured to conduct a second current in the first direction;
- a third source/drain region on a first side of the second channel region;
- and
- a fourth source/drain region on a second side of the second channel region;
- a second gate extending in the second direction and comprising the gate material disposed on each of the at least one second semiconductor slab in the second channel region;
- and
- a second gate cut extending through the second gate adjacent to the second channel region of the at least one second semiconductor slab in the second direction,
- wherein:
- the first gate cut is configured to cause the first gate to exert a first force in the second direction and a second force in the third direction on the first channel region of the at least one first semiconductor slab;
- the second gate cut is configured to cause the second gate to exert a third force in the second direction and a fourth force in the third direction on the second channel region of the at least one second semiconductor slab;
- and
- the first gate cut comprises a first gate cut wedge disposed in the insulation layer, the first gate cut wedge configured to cause the insulation layer to exert the second force on the first channel region in the third direction.
20 more elements
Dependencies are inferred from the claim text.