Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer

A method of forming CMOS devices featuring a channel region formed in a selectively grown, composite silicon layer, wherein said composite silicon layer is comprised of at least a strained SiGe layer and an overlying silicon layer, comprising the steps of:

• providing a first region of said semiconductor substrate to be used as an NMOS region, and providing a second region of said semiconductor substrate to be used as a PMOS region;
• forming shallow trench isolation (STI) regions in top portions of said semiconductor substrate, with a top portion of each STI region featuring tapered sides;
• forming a P well region in a top portion of said NMOS region, and forming an N well region in a top portion of said PMOS region;
• selectively depositing a composite silicon layer on the top surface of said P well region and on the top surface of said N well region, with said composite silicon layer featuring tapered sides, resulting in V-groove openings located between said tapered sides of said STI regions and tapered sides of said composite silicon layer, and with said composite silicon layer comprised of a silicon layer, a strained SiGe layer, and an overlying silicon layer;
• depositing an insulator layer;
• removing portion of insulator layer from the top surface of said composite insulator layer resulting in insulator filled V-grooves located between said STI regions and said composite silicon layer;
• and
• thermally oxidizing a top portion of said overlying silicon layer to form a silicon dioxide gate insulator layer on a bottom portion of said overlying silicon layer.