G11C 7/18
Bit line organisation
Official title: Bit line organisation; Bit line lay-out
G11C7/18 (Bit line organisation) appears on 2,604 US grants and 2,331 published applications in this corpus.
Search patents in G11C- Granted patents
- 2,604
- Published applications
- 2,331
- Assignees
- 374
- Inventors
- 3,255
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 0 | 0 |
| 1986 | 6 | 0 |
| 1987 | 8 | 0 |
| 1988 | 1 | 0 |
| 1989 | 13 | 0 |
| 1990 | 7 | 0 |
| 1991 | 12 | 0 |
| 1992 | 7 | 0 |
| 1993 | 12 | 0 |
| 1994 | 23 | 0 |
| 1995 | 16 | 0 |
| 1996 | 24 | 0 |
| 1997 | 28 | 0 |
| 1998 | 46 | 0 |
| 1999 | 57 | 0 |
| 2000 | 68 | 0 |
| 2001 | 67 | 34 |
| 2002 | 75 | 65 |
| 2003 | 90 | 100 |
| 2004 | 90 | 98 |
| 2005 | 89 | 101 |
| 2006 | 79 | 83 |
| 2007 | 94 | 109 |
| 2008 | 86 | 110 |
| 2009 | 89 | 90 |
| 2010 | 95 | 87 |
| 2011 | 76 | 64 |
| 2012 | 69 | 64 |
| 2013 | 70 | 82 |
| 2014 | 89 | 87 |
| 2015 | 98 | 80 |
| 2016 | 82 | 72 |
| 2017 | 72 | 60 |
| 2018 | 67 | 68 |
| 2019 | 88 | 118 |
| 2020 | 125 | 108 |
| 2021 | 108 | 142 |
| 2022 | 101 | 113 |
| 2023 | 117 | 147 |
| 2024 | 115 | 104 |
| 2025 | 93 | 94 |
| 2026 | 44 | 51 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Static random-access memory devices with angled transistors8 Sep 2026US 12,733,146 B2Intel Corporation
- Reducing capacitive loading of memory system based on switches25 Aug 2026US 12,718,854 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Vertical memory device with a double word line structure18 Aug 2026US 12,712,014 B2SK hynix Inc.
- Bit-line resistance reduction11 Aug 2026US 12,707,648 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Memory subarray and interconnection circuit arrangement4 Aug 2026US 12,700,441 B2Micron Technology, Inc.
- Memory device8 Oct 2026US 2026/0311733 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Multi-wafer bonding for nand scaling1 Oct 2026US 2026/0305424 A1SanDisk Technologies LLC
- Volatile memory device24 Sep 2026US 2026/0290442 A1Samsung Electronics Co., Ltd.
- Memory core circuit having cell on periphery (cop) structure and memory device including the same27 Aug 2026US 2026/0253632 A1Samsung Electronics Co., Ltd.
- Memory module with independently accessible memory channels formed across multiple memory dies13 Aug 2026US 2026/0240046 A1Sunrise Memory Corporation
Most cited
By later US patents
- Segmented column memory array801US 5,315,541 ASunDisk Corporation · 1994
- Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines462US 6,166,942 AMicron Technology, Inc. · 2000
- DRAM having bidirectional global bit lines453US 5,367,488 AGoldstar Electron Co., Ltd. · 1994
- Dynamic memory with isolated digit lines445US 5,506,811 AMicron Technology, Inc. · 1996
- Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout442US 4,977,542 AMitsubishi Denki Kabushiki Kaisha · 1990