Memory subarray and interconnection circuit arrangement

An apparatus, comprising:

• an array of memory cells comprising a subarray, wherein the subarray comprises:
• a first interconnect extending in a first direction and traversing at least a first portion of a first substrate of the subarray, the first interconnect coupled with the first portion of the first substrate and a first interconnection layer, wherein the first interconnect is a socket feed-through region that does not electrically contact any word line or digit line;
• and
• a second interconnect extending in a second direction and traversing at least a second portion of the first substrate of the subarray, the second interconnect coupled with the second portion of the first substrate and the first interconnection layer, wherein the second interconnect is a socket feed-through region that does not electrically contact any word line or digit line and the first portion and the second portion of the first substrate comprise at least a first edge and a second edge of the first substrate, respectively, and wherein the first substrate comprises complementary metal-oxide-semiconductor circuitry under arrays (CuA) that is adjacent to the first edge and the second edge.