US 5,315,541 AGranted

Segmented column memory array

AssigneeSunDisk Corporation

InventorsEliyahou Harari, Sanjay Mehrotra

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Abstract

In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell's pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.

Claims11

Dependent claims

In an EPROM or EEPROM of Flash EEPROM integrated circuit memory device, including a two-dimensional array of memory cells organized in rows and columns, each memory cell having a gate, a source and a drain, said two-dimensional array having a word line connected to all the gates in each row, said integrated circuit memory device comprising:

a plurality of segmented arrays formed by partitioning the two-dimensional array along the column direction, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to all the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;
cell accessing means connectable to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising:
a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;
first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;
each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails;
and
said second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;
thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines.

5 more elements

partitioning the two-dimensional array along the column direction to form a plurality of segmented arrays, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to all the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;
selectively connecting a cell accessing means to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising:
a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;
first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;
each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails;
and
each second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;
thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines;
and
said two-dimensional array being segmented that a segmented column therein containing a defect is isolated therein.

7 more elements

partitioning the two-dimensional array along the column direction to form a plurality of segmented arrays, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to al the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;
selectively connecting a cell accessing means to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising:
a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;
first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;
each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails;
and
each second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;
thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines;
and
said two-dimensional array having segmented arrays with independent segmented bit lines that additional capacitance imparted from other segmented bit lines is avoided.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/919,715Filed 24 Jul 1992
Granted: 24 May 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 16/0491
Using variable threshold transistors, e.g. FAMOS: virtual ground arrays