Reducing capacitive loading of memory system based on switches
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
Life of this patent
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Abstract
Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
Claims20
A memory array, comprising:
- a first subset of memory cells;
- a first switch including:
- a first electrode connected to first electrodes of the first subset of memory cells, and
- a second electrode connected to a first global bit line;
- and
- a second switch including:
- a first electrode connected to second electrodes of the first subset of memory cells, and
- a second electrode connected to a first global select line.
A memory array, comprising:
- a first subset of memory cells;
- a second subset of memory cells disposed above the first subset of memory cells;
- a first switch coupling the first subset of memory cells to a first global line;
- a second switch coupling the first subset of memory cells to a second global line;
- a third switch coupling the second subset of memory cells to the second global line;
- and
- a fourth switch coupling the second subset of memory cells to a third global line;
- wherein the first to third global lines all extend along a first lateral direction.
A memory array, comprising:
- a first subset of memory cells vertically arranged with respect to one another;
- a second subset of memory cells vertically arranged with respect to one another, the second subset of memory cells is vertically disposed above the first subset of memory cells;
- a first switch coupling the first subset of memory cells to a first global line, the first global line vertically disposed below the first subset of memory cells;
- a second switch coupling the first subset of memory cells to a second global line, the second global line vertically disposed above the first subset of memory cells;
- a third switch coupling the second subset of memory cells to the second global bit line;
- and
- a fourth switch coupling the second subset of memory cells to a third global line, the third global line vertically disposed above the second subset of memory cells;
- wherein the first to third global lines all extend along a first lateral direction.
Dependencies are inferred from the claim text.