US 12,733,146 B2 · Static random-access memory devices with angled transistors

Abstract

SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a substrate having a first face and an opposing second face;
and
a memory cell comprising a plurality of transistors,
wherein:
a first set of one or more transistors of the plurality of transistors is over the first face,
a second set of one or more transistors of the plurality of transistors is over the second face, coupled with one or more transistors of the first set with one or more interconnects that extend through the substrate, and
a projection of a longitudinal axis of a transistor of the first set or a transistor of the second set onto the substrate is at an angle between about 10 and 80 degrees with respect to one or more edges of the substrate.

4 more elements

An integrated circuit (IC) device, comprising:

a die;
a first semiconductor structure over the die, the first semiconductor structure having a first portion and a second portion at an angle less than 180 degrees with respect to one another;
a second semiconductor structure over the die, the second semiconductor structure having a first portion and a second portion at an angle less than 180 degrees with respect to one another;
a plurality of transistors, each comprising a gate, a first region, and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region, and wherein the plurality of transistors includes transistors M1, M2, M3, and M4;
wherein:
a channel portion of the transistor M1 is in the first portion of the first semiconductor structure,
a channel portion of the transistor M2 is in the first portion of the second semiconductor structure,
a channel portion of the transistor M3 is in the second portion of the first semiconductor structure,
a channel portion of the transistor M4 is in the second portion of the second semiconductor structure,
the first region of the transistor M1 is coupled with the first region of the transistor M2,
the gate of the transistor M1 is coupled with the gate of the transistor M2,
the first region of the transistor M3 is coupled with the first region of the transistor M4, and
the gate of the transistor M3 is coupled with the gate of the transistor M4.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/312,847Filed 5 May 2023 · continuation

Priority

22 Jun 2022

Published

US 2023/0422463 A128 Dec 2023

Granted

8 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 10/125
Comprising a MOSFET load element: the MOSFET being a thin film transistor [TFT]
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts

Static random-access memory devices with angled transistors

Life of this patent

Static random-access memory devices with angled transistors

Life of this patent

Abstract

Claims20