US 6,166,942 A · Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Abstract

A DRAM architecture configures memory cells into a predetermined number of arrays. Each array has its own row decoders and sense amplifiers. A data path circuit containing local drivers and data read and write lines is associated with each of the arrays in a first direction. The respective connections between the array and data path circuit utilize IO lines that are considerably shorter than the IO lines used in prior art architectures. Using this unique arrangement of data path circuits and memory arrays as a building block, a DRAM architecture of increased capacity can be constructed by simply placing additional data paths and memory arrays on to the semiconductor device in a second direction orthogonal to the first direction.

Claims42

Dependent claims

A memory circuit comprising:

a first pair of transfer circuits arranged adjacent to each other in a first direction, each transfer circuit being connected to a respective input circuit and output circuit;
and
at least one block of memory cells connected to each transfer circuit, each block of memory cells being arranged in said first direction with respect to its associated transfer circuit, said blocks of memory cells being arranged such that said first pair of transfer circuits and their associated input and output circuits are located between said blocks of memory cells with respect to said first direction, each transfer circuit for transferring data between its associated input and output circuits and block of memory cells.

A memory circuit comprising:

a first block of memory cells connected to a first input circuit and a first output circuit through a first transfer circuit, said first input, output and transfer circuits being positioned adjacent said first block of memory cells in a first direction and being on a same side of said first block of memory cells;
and
a second block of memory cells connected to a second input circuit and a second output circuit through a second transfer circuit, said second input, output and transfer circuits being positioned adjacent said second block of memory cells in said first direction and being on a same side of said second block of memory cells such that said first and second input, output and transfer circuits are positioned between said first and second blocks of memory cells with respect to said first direction.

A computer system comprising:

a processor;
and
a semiconductor device connected to said processor, said semiconductor device comprised of memory modules connected to a column decoder, each of said memory modules comprising:
a first pair of transfer circuits arranged adjacent to each other in a first direction, each transfer circuit being connected to a respective input circuit and output circuit;
and
at least one block of memory cells connected to each transfer circuit, each block of memory cells being arranged in said first direction with respect to its associated transfer circuit, said blocks of memory cells being arranged such that said first pair of transfer circuits and their associated input and output circuits are located between said blocks of memory cells with respect to said first direction, each transfer circuit for transferring data between its associated input and output circuits and block of memory cells.

3 more elements

A method of operating a memory circuit comprising a first data read circuit connected to at least first and second memory arrays by a first selection circuit, said method comprising:

propagating a signal to cause the first selection circuit to connect the first memory array to the first data read circuit;
propagating a signal to activate a first word line connected to a row of memory cells in the first memory array;
propagating a signal to activate at least a first digit line connected to a column of memory cells in the first memory array having the first word line activated;
transferring data from memory cells associated with and connected to the activated first word line and first digit line;
propagating a signal to cause the first selection circuit to connect the second memory array to the first data read circuit;
propagating a signal to activate a second word line connected to a row of memory cells in the second memory array;
propagating a signal to activate at least a second digit line connected to a column of memory cells in the second memory array having the second word line activated;
and
transferring data from memory cells associated with and connected to the activated second word line and second digit line.

6 more elements

A method of operating a memory circuit comprising a first data write circuit connected to at least first and second memory arrays by a first selection circuit, said method comprising:

propagating a signal to cause the first selection circuit to connect the first memory array to the first data write circuit;
propagating a signal to activate a first word line connected to a row of memory cells in the first memory array;
propagating a signal to activate at least a first digit line connected to a column of memory cells in the first memory array having the first word line activated;
transferring data to memory cells associated with and connected to the activated first word line and first digit line;
propagating a signal to cause the first selection circuit to connect the second memory array to the first data write circuit;
propagating a signal to activate a second word line connected to a row of memory cells in the second memory array;
propagating a signal to activate at least a second digit line connected to a column of memory cells in the second memory array having the second word line activated;
and
transferring data to memory cells associated with and connected to the activated second word line and second digit line.

6 more elements

Dependencies are inferred from the claim text.

Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Life of this patent

Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Life of this patent

Abstract

Claims42