US 2026/0240046 A1 · MEMORY MODULE WITH INDEPENDENTLY ACCESSIBLE MEMORY CHANNELS FORMED ACROSS MULTIPLE MEMORY DIES

Abstract

In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors. In other embodiments, a memory module includes multiple semiconductor memory dies coupled to a memory controller where the semiconductor memory dies are partitioned into independently accessible memory channels with each memory channel being formed across the multiple semiconductor memory dies.

Claims20

Dependent claims

A memory module, comprising:

a plurality of semiconductor memory dies, each semiconductor memory die comprising three-dimensional arrays of storage transistors that are divided into a plurality of partitions, wherein corresponding partitions across the plurality of semiconductor memory dies form a memory channel and the plurality of partitions across the plurality of semiconductor memory dies form a first number of independently accessible memory channels;
and
a memory controller die comprising a memory control circuitry for accessing and operating the plurality of semiconductor memory dies, the plurality of semiconductor memory dies being connected to the memory controller die through a set of interconnect structures, wherein the memory control circuitry comprises a first number of channel controllers, each channel controller being coupled to operate one of the memory channels to perform memory operations on the storage transistors associated with the respective memory channel independent of the other memory channels and in parallel with memory operations being performed on the storage transistors of the other memory channels.

Dependencies are inferred from the claim text.

Memory module with independently accessible memory channels formed across multiple memory dies

Life of this patent

Memory module with independently accessible memory channels formed across multiple memory dies

Life of this patent

Abstract

Claims20