Vertical memory device with a double word line structure
AssigneeSK hynix Inc.
InventorsSeung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
Life of this patent
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Abstract
A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.
Claims13
A memory device, comprising:
- a memory cell array including a plurality of memory cells,
- wherein each of the memory cells comprises:
- a capacitor comprising a lateral cylindrical shaped structure;
- an active layer coupled to the capacitor;
- and
- a pair of word lines comprising a lower word line disposed under the active layer and an upper word line disposed over the active layer.
Dependencies are inferred from the claim text.