US 4,977,542 A · Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

Abstract

An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

Claims21

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns for storing information charge;
a plurality of bit line pairs, each comprising a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;
a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;
read means for selecting any of said word lines by applying a potential thereto, and reading the respective information charges of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;
a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of each said bit line pair when said read means reads the information charges of the memory cells;
and
potential applying means for applying a potential for compensating for change in a potential of the bit lines to said bit lines, said change being caused by rise of a potential of the word line selected by said read means.

4 more elements

A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns, for storing information charge;
a first memory cell area where part of said memory cells are formed;
a second memory cell area where another part of said memory cells are formed;
a first dummy cell area formed between said first memory cell area and said second memory cell area;
a third memory cell area formed adjacent to said second memory cell area, part of said memory cells being formed in said third memory cell area;
a fourth memory cell area where part of said memory cells are formed;
a second dummy cell area formed between said third memory cell area and said fourth memory cell area;
a plurality of bit line pairs each including a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;
a plurality of word lines provided corresponding to the respective columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;
read means for selecting any of said word lines by applying a potential thereto, and reading the information charge of each of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;
a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means;
a plurality of dummy cells, at least one dummy cell being provided for each bit line in said first or second dummy cell area;
a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs, and connected to the corresponding dummy cells, a predetermined potential being applied to said dummy word lines;
and
potential cancel means responsive to the selection of the word line by said read means, for cancelling the application of said predetermined potential to the dummy word line connected to any of the dummy cells provided with respect to the bit line to which the memory cell connected to the selected word line is connected.

12 more elements

A semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns, for storing information charge;
a first memory cell area where part of said memory cells are formed;
a second memory cell area formed adjacent to said first memory cell area part of said memory cells being formed in said second memory cell area;
a third memory cell area where part of said memory cells are formed;
a first dummy cell area formed between said second and third memory cell areas;
a fourth memory cell area formed adjacent to said first dummy cell area, part of said memory cells being formed in said fourth memory cell area;
a fifth memory cell area adjacent to said fourth memory cell area, part of said memory cells being formed in said fifth memory cell area;
a sixth memory cell area formed adjacent to said fifth memory cell area, part of said memory cells being formed in said sixth memory cell area;
a seventh memory cell area where part of said memory cells are formed;
a second dummy cell area formed between said sixth and seventh memory cell areas;
an eighth memory cell area formed adjacent to said memory cell area, part of said memory cells being formed in said eighth memory cell area;
a plurality of bit line pairs each including a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;
a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;
read means for selecting any of said word lines by applying a potential thereto, and reading the information charge of each of the memory cells connected to the selected word line onto one of the bit lines of each said bit line pair;
a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means;
a plurality of dummy cells, at least one dummy cell being provided for each said bit line in said first or second dummy cell area;
a plurality of dummy word lines provided corresponding to the respective dummy cells in a direction intersecting with said bit line pairs, and connected to the corresponding dummy cells, a predetermined potential being applied to said dummy word lines;
and
potential cancel means responsive to the selection of the word line by said read means, for cancelling the application of said predetermined potential to the dummy word line connected to any of the dummy cells provided with respect to the bit line to which the memory cell connected to the selected word line is connected.

16 more elements

A semiconductor memory device comprising:

a semiconductor substrate having a main surface;
a plurality of memory cells formed on the main surface of said semiconductor substrate and arranged in a matrix of rows and columns, for storing information charge;
an interlayer insulating film formed on the main surface of said semiconductor substrate to cover said memory cells;
a plurality of bit line pairs formed on said interlayer insulating film, each said bit line pair being formed of a pair of bit lines having at least one twisted portion, the respective bit lines being provided corresponding to the rows of said memory cells and connected to the memory cells of the corresponding rows;
a plurality of word lines provided corresponding to the columns of said memory cells in a direction intersecting with said bit line pairs, and connected to the memory cells of the corresponding columns;
read means for selecting any of said word lines by applying a potential thereto, and reading the information charges of the memory cells connected to the selected word line onto the respective bit lines of said bit line pairs;
and
a plurality of sense amplifiers provided corresponding to the respective bit line pairs, each said sense amplifier detecting a potential difference appearing between the bit lines of the corresponding bit line pair when the information charges of the memory cells are read by said read means,
one bit line of each said pair being connected at said twisted portion through a conductor having a section formed like the letter V.

6 more elements

Dependencies are inferred from the claim text.

Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

Life of this patent

Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

Life of this patent

Abstract

Claims21