Bit-line resistance reduction

A method of forming an integrated chip structure, comprising:

• forming a plurality of memory devices over a substrate;
• forming a first inter-level dielectric (ILD) layer to laterally surround the plurality of memory devices;
• forming a peripheral lower interconnect within the first ILD layer;
• forming a first dielectric stack over the plurality of memory devices and the first ILD layer;
• forming a common electrode within the first dielectric stack, the common electrode laterally extending over the plurality of memory devices;
• forming a second dielectric stack over the first dielectric stack and the common electrode;
• forming a plurality of vias within the second dielectric stack and on the common electrode;
• forming a second ILD layer over the second dielectric stack and the plurality of vias;
• forming a peripheral via extending through a part of the second ILD layer, wherein the peripheral via is laterally outside of the plurality of memory devices and the common electrode, wherein the peripheral via has a bottommost surface that is at an equal height over the substrate as a bottommost surface of the common electrode, and wherein the peripheral lower interconnect contacts the bottommost surface of the peripheral via along an interface that is a non-zero distance vertically below a top of the common electrode, and wherein the peripheral lower interconnect laterally extends past an outermost sidewall of the peripheral via;
• and
• forming an interconnect wire within the second ILD layer and on the plurality of vias.

A method of forming an integrated chip structure, comprising:

• forming a plurality of memory devices over a substrate as viewed in a cross-sectional view;
• forming a common electrode over the plurality of memory devices and continuously extending past outermost edges of the plurality of memory devices;
• forming a local interconnect over the plurality of memory devices, wherein the common electrode is vertically between the local interconnect and the plurality of memory devices and is coupled to the local interconnect by way of a plurality of local interconnect vias;
• forming a plurality of interconnect vias over the local interconnect;
• forming a bit-line over the local interconnect, the bit-line extending in parallel to the local interconnect and past opposing ends of the local interconnect;
• and
• wherein the local interconnect is coupled to the bit-line by the plurality of interconnect vias, the plurality of interconnect vias being disposed between a top of the local interconnect and a bottom of the bit-line.