Memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng CHANG, Chia-En HUANG, Yi-Ching LIU, Yih WANG
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Abstract
A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.
Claims20
A memory device, comprising:
- a first memory array, comprising:
- a first switch and a plurality of first memory cells that are stacked vertically in layers;
- a second switch and a plurality of second memory cells that that are stacked vertically in the layers and adjacent to the first switch and the plurality of first memory cells horizontally;
- and
- a first continuous conductive line extending along a first direction and folding back along a second direction opposite to the first direction to form a dual-track parallel arrangement, and further coupled to the plurality of first memory cells and the plurality of second memory cells.
A memory device, comprising:
- a first memory array and a second memory array each comprising a plurality of pairs of switches and a plurality of memory cells in a plurality of columns, wherein each pair in the plurality of pairs of switches are coupled to two columns of memory cells in the plurality of memory cells;
- a first word line and a second word line that are coupled to memory cells arranged in the same rows of the first and second memory arrays;
- and
- a third word line coupling the first word line to the second word line and configured to transmit a first word line signal to the memory cells arranged in the same rows of the first and second memory arrays.
A method, comprising:
- in a first read operation of a first memory cell in a first column, coupling a first data line, extending from a second column next to the first column, to a first end of the first memory cell, and coupling a second data line to a second end of the first memory cell, wherein a first portion of the second data line extends in the first column;
- and
- in a second read operation of a second memory cell in a second column, coupling the first data line, having a portion extending in the second column, to a first end of the second memory cell, and coupling the second data line, having a second portion extending from the first column to the second column, to a second end the second memory cell.
Dependencies are inferred from the claim text.