Memory core circuit having cell on periphery (cop) structure and memory device including the same

A memory core circuit comprising:

• a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns;
• and
• a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit of the plurality of sub peripheral circuits is disposed under a corresponding sub cell array of the plurality of sub cell arrays,
• wherein the memory cell array further comprises:
• an interlayer insulation film;
• a conductive line disposed below the interlayer insulation film;
• a channel structure extending through the interlayer insulation film and electrically coupled to the conductive line, the channel structure comprising a penetration portion extending in a vertical direction and a pair of extension portions extending from the penetration portion;
• a first gate electrode disposed adjacent to a first one of the pair of extension portions;
• a second gate electrode disposed adjacent to a second one of the pair of extension portions,
• wherein the channel structure comprises an oxide semiconductor material, and the penetration portion and the pair of extension portions form a continuous channel region configured to form two transistors sharing the penetration portion.

A memory device comprising:

• a memory core circuit;
• and
• device peripheral circuits configured to control the memory core circuit,
• wherein the memory core circuit comprises:
• a memory cell array comprising a plurality of sub cell arrays that are arranged in a first matrix comprising a plurality of array rows and a plurality of array columns;
• and
• a core control circuit comprising a plurality of sub peripheral circuits that are arranged in a second matrix comprising the plurality of array rows and the plurality of array columns, wherein each sub peripheral circuit of the plurality of sub peripheral circuits is disposed under a corresponding sub cell array of the plurality of sub cell arrays, and
• wherein the memory cell array further comprises:
• a conductive line extending in a column direction on a substrate;
• an interlayer insulation film that includes a cell trench extending in a row direction on the substrate;
• a first gate electrode and a second gate electrode that are spaced apart from each other in the column direction and each extend in the row direction, inside the cell trench;
• a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode;
• and
• a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.