G11C 7/1012
Data reordering during input/output
Official title: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
G11C7/1012 (Data reordering during input/output) appears on 992 US grants and 965 published applications in this corpus.
Search patents in G11C- Granted patents
- 992
- Published applications
- 965
- Assignees
- 204
- Inventors
- 1,521
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 2 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 9 | 0 |
| 1999 | 8 | 0 |
| 2000 | 20 | 0 |
| 2001 | 28 | 12 |
| 2002 | 15 | 24 |
| 2003 | 21 | 10 |
| 2004 | 26 | 23 |
| 2005 | 18 | 28 |
| 2006 | 32 | 22 |
| 2007 | 22 | 33 |
| 2008 | 16 | 22 |
| 2009 | 21 | 34 |
| 2010 | 19 | 27 |
| 2011 | 28 | 29 |
| 2012 | 27 | 29 |
| 2013 | 28 | 26 |
| 2014 | 26 | 29 |
| 2015 | 38 | 34 |
| 2016 | 40 | 36 |
| 2017 | 41 | 48 |
| 2018 | 46 | 47 |
| 2019 | 69 | 53 |
| 2020 | 48 | 49 |
| 2021 | 59 | 68 |
| 2022 | 61 | 75 |
| 2023 | 69 | 66 |
| 2024 | 67 | 61 |
| 2025 | 51 | 50 |
| 2026 | 26 | 30 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Non-volatile programmable logic device based on multi-chip package15 Sep 2026US 12,737,520 B2iCometrue Company Ltd.
- Circuit and method for optimization with digital adder, analog adder, and multiplier15 Sep 2026US 12,738,303 B2Huawei Technologies Co., Ltd.
- Memory circuit architecture with multiplexing between memory banks1 Sep 2026US 12,725,640 B2QUALCOMM Incorporated
- Memory system and memory chip25 Aug 2026US 12,717,732 B2Etron Technology, Inc.
- Configurable data protection circuitry for memory devices25 Aug 2026US 12,718,850 B2Micron Technology, Inc.
- Memory shifting circuit8 Oct 2026US 2026/0311796 A1
- Semiconductor device1 Oct 2026US 2026/0301827 A1Kioxia Corporation
- Memory device generating voltage responsive to temperature and method of operating the same10 Sep 2026US 2026/0268949 A1SK hynix Inc.
- Read operations for a memory array and register13 Aug 2026US 2026/0237411 A1Micron Technology, Inc.
- Storage circuit13 Aug 2026US 2026/0237412 A1Arm Limited
Most cited
By later US patents
- Semiconductor memory device allowing high-speed operation of internal data buses455US 6,172,918 B2Mitsubishi Denki Kabushiki Kaisha · 2001
- Apparatus for synchronously generating clock signals in a data processing system430US 5,243,703 ARambus Inc. · 1993
- Memory system having synchronous-link DRAM (SLDRAM) devices and controller383US 6,442,644 B1Advanced Memory International, Inc. · 2002
- Integrated circuit I/O using high performance bus interface325US 5,319,755 ARambus Inc. · 1994
- Memory circuitry having bus interface for receiving information in packets and access time registers282US 5,606,717 ARambus Inc. · 1997