Non-volatile programmable logic device based on multi-chip package

A multichip package comprising:

• a first interconnection scheme comprising a first insulating dielectric layer, a first interconnection metal layer over the first insulating dielectric layer and a second insulating dielectric layer over the first interconnection metal layer and first insulating dielectric layer;
• a plurality of first metal bumps at a bottom of the multichip package and under and in contact with the first interconnection scheme;
• a first semiconductor chip over the first interconnection scheme, wherein the first interconnection scheme extends horizontally across under a right edge of the first semiconductor chip, wherein the first semiconductor chip comprises a first metal pad at a top of the first semiconductor chip and a first polymer layer at the top of the first semiconductor chip and in contact with a sidewall of the first metal pad;
• a second polymer layer over the first interconnection scheme, at a first horizontal level same as the first semiconductor chip and in contact with a sidewall of the first semiconductor chip;
• a metal post vertically in the second polymer layer, over and coupling to the first interconnection scheme and at the first horizontal level, wherein the metal post provides vertical connection and has a sidewall in contact with the second polymer layer;
• a second interconnection scheme over the first semiconductor chip, second polymer layer and metal post, wherein the second interconnection scheme extends horizontally across over the right edge of the first semiconductor chip and couples vertically to the first interconnection scheme through the metal post, wherein the second interconnection scheme comprises a third insulating dielectric layer at a top of the second interconnection scheme and over the first semiconductor chip and second polymer layer, and the second interconnection scheme further comprises a plurality of second metal pads at the top of the second interconnection scheme, wherein each of the plurality of second metal pads has a first portion in an opening in the third insulating dielectric layer and a second portion over the opening in the third insulating dielectric layer and on a top surface of the third insulating dielectric layer, wherein said each of the plurality of second metal pads comprises a first copper layer and a first adhesion metal layer at a bottom of the first copper layer;
• and
• a first chip-over-chip package over and coupling to the second interconnection scheme, wherein the first chip-over-chip package comprises a second semiconductor chip, a third semiconductor chip over the second semiconductor chip and a third polymer layer at a second horizontal level same as the third semiconductor chip, wherein a left sidewall of the third polymer layer at a left edge of the first chip-over-chip package is vertically over the second interconnection scheme and has a first horizontal distance from a left sidewall of the second polymer layer at a left edge of the multichip package, wherein the first chip-over-chip package comprises a plurality of second metal bumps at a bottom of the first chip-over-chip package and each bonded to one of the plurality of second metal pads.