US 6,442,644 B1 · Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Abstract

A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Claims40

Dependent claims

A Synchronous-Link Dynamic Random Access Memory (SLDRAM) System comprising:

(a) a command module for issuing unicast command packets directed to uniquely addressable ones of plural memory units and for issuing multicast command packets directed to addressable collections of said memory units;
(b) a command link for carrying the command packets;
(c) one or more data links for carrying data corresponding to packet-commanded data-transfer actions;
and
(d) one or more, in-circuit programmably-calibratable SLDRAM modules each having one or more of said addressable memory units, where each SLDRAM module is capable of interfacing with the command link and at least one of the data links for appropriately responding to informational queries provided by command packets, for further appropriately responding to tuning (adjustment, or calibrating) commands provided by command packets, and for yet further appropriately responding to data addressing and other data-transfer-related commands provided by command packets.

2 more elements

A method for initializing a SLDRAM system having one or more, in-circuit programmably-calibratable SLDRAM modules, said method comprising the steps of:

(a) first initializing the SLDRAM system by broadcasting from a reference location a predefined first synchronization sequence over command/address lines and data lines of the system while simultaneously and synchronously outputting from the reference location a continuously-running clock train over one or more clock lines of the system for allowing one or more SLDRAM modules present in the system to each self-adjust local command-receiving circuits and data-receiving circuits of the SLDRAM module to synchronously recognize the predefined first synchronization sequence at the locality of the SLDRAM module;
(b) second initializing the SLDRAM system by sequentially assigning identification codes to individually-addressable, memory units within the in-system SLDRAM modules;
(c) third initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to adjust output levels of the SLDRAM module's data-clock driving circuits and data-line driving circuits to levels acceptable to an in-circuit memory controller;
(d) fourth initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to respectively output a predefined second synchronization sequence over the data lines of the system while simultaneously and synchronously outputting from the commanded SLDRAM module, a continuously-running clock train over one or more data-clock lines of the system, this for allowing the in-circuit memory controller to command adjustments (e.g., individual phase changes) to local data-outputting circuits and local data-clock outputting circuits of the sequence-outputting SLDRAM module So that the memory controller will be able to synchronously recognize the predefined second synchronization sequence at the locality of the memory controller;
and
(e) fifth initializing the SLDRAM system by sequentially determining data read and data write latency times of respective ones of the in-circuit, individually-addressable, memory units.

3 more elements

A packaged memory part comprising:

a plurality of at least sixty-four, sequentially ordered, interconnection terminals for interconnecting internal circuitry of the memory part with external circuitry,
wherein said sequentially ordered, interconnection terminals of the memory part are arranged as a first group of odd-enumerable terminals and a second group of even-enumerable terminals provided along a periphery of the memory part, and
wherein correspondence between said enumeration and signals carried by the respective interconnection terminals is as set forth in the following, two-column list in which terminal number is on the left and signal name is on the right:
1 Vdd
2 Vss
3 Vdd
4 Vss
5 TEST
6 LINKON
7 RESET#
8 LISTEN
9 Vdd
10 Vss
11 VddQ
12 VssQ
13 DQ17
14 DQ0
15 DQ1
16 DQ2
17 DQ3
18 DQ4
19 VddQ
20 VssQ
21 DQ5
22 DQ6
23 DQ7
24 DCLK0#
25 DCLK0
26 DCLK1#
27 DCLK1
28 CCLK#
29 CCLK
30 CA0
31 CA1
32 CA2
33 Vdd
34 Vss
35 CA3
36 CA4
37 CA5
38 CA6
39 CA7
40 CA8
41 CA9
42 FLAG
43 DQ8
44 DQ9
45 DQ10
46 VssQ
47 VddQ
48 DQ11
49 DQ12
50 DQ13
51 DQ14
52 DQ15
53 DQ16
54 VssQ
55 VddQ
56 Vss
57 Vdd
58 Vref
59 SI
60 SO
61 Vss
62 Vdd
63 Vss
64 Vdd.

64 more elements

An initialization method for use with one or more packaged memory parts of a memory system, wherein each memory part has a predefined number of sequentially ordered, interconnection terminals for interconnecting internal circuitry of the memory part with external circuitry, said external circuitry includes a command link, a serial link and one or more data links,

(53.1) wherein the command link is for carrying on lines thereof, a plurality of command link signals, including:
(53.1a) a first complementary pair of command clock signals identifiable respectively as CCLK and CCLK#;
(53.1b) a parallel set of at least ten command/address signals synchronized with the command clock signals, the command/address signals being representative at least of command packets and being identifiable respectively as CA0 through CA9;
(53.1c) a plurality of FLAG signals, each for identifying a start of a corresponding command packet;
(53.1d) a LISTEN signal for indicating when commands can be present on the command link;
(53.1e) a LINKON signal for indicating when the packaged memory part may enter a power-saving, shutdown mode;
and
(53.1f) a RESET# signal for indicating when the packaged memory part should enter a reset mode,
(53.2) wherein the serial link is for carrying a daisy-chained, set of serial signals including a SI signal and a SO signal;
(53.3) wherein at least one of said data links is for carrying on lines thereof, a plurality of data link signals, including:
(53.3a) first and second complementary pairs of data clock signals identifiable respectively as DCLK0, DCLK0#, DCLK1, and DCLK1#;
(53.3b) a parallel set of at least eighteen data signals synchronized with one of the complementary first and second pairs of said data clock signals, where at least a subset of the data signals are representative at least of data stored or to be stored in memory and where said at least eighteen data signals are individually identifiable respectively as DQ0 through DQ17;
and
(53.4) wherein each said memory part of the memory system includes at least respective SI and SO terminals for carrying the SI and SO signals, CA0 through CA9 terminals for respectively carrying the CA0 through CA9 signals, and DQ0 through DQ17 terminals for respectively carrying the DQ0 through DQ17 signals;
said initialization method comprising the steps of:
(a) applying a first activating signal to the SI terminal of each memory part of the memory system for initiating a respective first initialization operation in each memory part where the part auto-synchronizes itself to recognize a pre-defined synchronization pattern broadcast onto the CA and DQ lines from a reference location;
and
(b) after said first initialization operation completes in each memory part of the system, applying a second activating signal to the SI terminal of each memory part of the memory system for initiating a respective second initialization operation in each memory part wherein the part is individually tuned according to its respective position relative to the reference location.

15 more elements

A re-calibration method for use with one or more packaged and in-circuit resident memory parts of a memory system, wherein each said memory part includes a data-storing memory, and a configuration memory storing configuration indicia representing characteristics of the memory part, the configuration memory including a tunable portion, and said initialization method comprising the steps of:

(a) tuning the tunable portion of the configuration memory at a first time under initial, in-circuit conditions;
and
(b) re-tuning at least part of the tunable portion of the configuration memory at a second time wherein in-circuit conditions may have changed.

A method for initializing a SLDRAM system having one or more, in-circuit programmably-calibratable SLDRAM modules, said method comprising the steps of:

(a) first initializing the SLDRAM system by broadcasting from a reference location a predefined first synchronization sequence over command/address lines and data lines of the system while simultaneously and synchronously outputting from the reference location a continuously-running clock train over one or more clock lines of the system for allowing one or more SLDRAM modules present in the system to each self-adjust local command-receiving circuits and data-receiving circuits of the SLDRAM module to synchronously recognize the predefined first synchronization sequence at the locality of the SLDRAM module;
(b) second initializing the SLDRAM system by sequentially assigning identification codes to individually-addressable, memory units within the in-system SLDRAM modules;
(c) third initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to adjust output levels of the SLDRAM module's data-clock driving circuits and data-line driving circuits to levels acceptable to an in-circuit memory controller;
(d) fourth initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to respectively output a predefined second synchronization sequence over the data lines of the system while simultaneously and synchronously outputting from the commanded SLDRAM module, a continuously-running clock train over one or more data-clock lines of the system, this for allowing the in-circuit memory controller to command adjustments (e.g., individual phase changes) to local data-outputting circuits and local data-clock outputting circuits of the sequence-outputting SLDRAM module so that the memory controller will be able to synchronously recognize the predefined second synchronization sequence at the locality of the memory controller;
and
(e) fifth initializing the SLDRAM system by sequentially determining data read and data write latency times of respective ones of the in-circuit, individually-addressable, memory units.

3 more elements

Dependencies are inferred from the claim text.

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Life of this patent

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Life of this patent

Abstract

Claims40